Abstract: The present description concerns an electronic device comprising: a silicon layer, an insulating layer in contact with a first surface of the silicon layer, a transistor comprising source, drain, and body regions arranged in the silicon layer, and a gate region topping the body region and comprising a gate portion laterally extending beyond the source and drain regions, the body region being continued by a body contact region not covered with the gate region, and a region of extension of the body region being located under the gate portion; the device further comprising, under the gate portion, a partial insulating trench in the silicon layer extending from a second surface of the silicon layer down to a depth smaller than the thickness of the silicon layer.

Abstract: The present description concerns an electronic device comprising: —a silicon layer having a first surface and a second surface, —an insulating layer in contact with the first surface of the silicon layer, —at least one transistor comprising source, drain, and body regions arranged in the silicon layer, and a gate region topping the body region and comprising a gate portion laterally extending beyond the source and drain regions, the body region being continued by a body contact region not covered with the gate region, and a region of extension of the body region being located under the gate portion; the gate portion being less heavily doped than the rest of the gate region.

Abstract: A method for determining a CET mapping characterizing the capture and emission time of traps in a transistor for a given stress voltage and a given temperature, called an optimal CET mapping, this determination being made from an experimental measurement of the time course of the change in the threshold voltage V_TH for the same stress voltage and the same temperature and from a distribution function of the traps, the distribution function may be defined by N_par parameters. More particularly, the method implements a genetic algorithm whose parameters are regularly updated in order to optimize the computation time while decreasing the risk of reaching a local minimum in the determination of the optimal CET mapping.

Abstract: A method for measuring the changes of the electrical performance of an FDSOI transistor between a first and a second state of the transistor after an operating period t1, including the following steps: measurement of the transistor's capacities C1 and C2 respectively in the first and second states, according to a voltage VFG applied between the gate and the source and drain areas, determination, in relation to characteristic C1(VFG) varying between a maximum value Cmax and a minimum value Cmin, with three inflection points, of an ordinate value Cplat of C1(VFG) at the second inflection point of C1(VFG), and of two abscissa values VUpper(0) and VLower(0) of C1(VFG) according to equations VUpper(0)=C1?1((Cmax+Cplat)/2) and VLower(0)=C1?1((Cmin+Cplat)/2), determination, from characteristic C2(VFG), of two abscissa values VUpper(t1) and VLower(t1) of C2(VFG) according to equations VUpper(t1)=C2?1((Cmax+Cplat)/2) and VLower(t1)=C2?1((Cmin+Cplat)/2), determination of variations of defect densities ?Dit1, ?Dit2 b

Abstract: A method for evaluating the electric performances of an FDSOI transistor, including the steps of: measuring capacitance and/or conductance of the FDSOI transistor, by applying a voltage VBG>0 on a substrate composed of semiconductor of the FDSOI transistor when the FDSOI transistor is NMOS or a voltage VBG<0 on the substrate composed of semiconductor of the FDSOI transistor when the FDSOI transistor is PMOS, depending on a voltage VFG applied between a gate and source and drain regions of the FDSOI transistor.

Abstract: A method for evaluating the electric performances of an FDSOI transistor, including the steps of: measuring the capacitance and/or the conductance of the FDSOI transistor, by applying a rear voltage VBG>0 or VBG<0 on the substrate of the transistor, depending on a front voltage VFG applied on the gate of the transistor, calculating the theoretical values of the capacitance and/or the conductance of a transistor modeled by an electric circuit equivalent to the FDSOI transistor, for different selected theoretical values of defect densities Dit1, Dit2 at the dielectric-semiconductor interfaces of the modeled transistor, determining the real values of Dit1, Dit2 at the corresponding interfaces of the FDSOI transistor by a comparison between the measured values of the capacitance and/or the conductance of the FDSOI transistor and the calculated theoretical values of the capacitance and/or the conductance of the modeled transistor.