Abstract: Method includes identifying, while programming sets of pages to dice of memory device, multiple sets of pages experiencing a variation in temporal voltage shift satisfying a threshold criterion; partitioning a set of pages of the multiple sets of pages into a set of fixed-length partitions; storing, in a metadata table, a value to indicate a size of each fixed-length partition; receiving a read operation directed at a page of the set of pages; determining, based on a logical block address of the read operation and on the value that indicates the size of each fixed-length partition, a partition of the set of fixed-length partitions to which the read operation corresponds; and searching within the metadata table to determine a block family to which the partition is assigned, wherein the searching is based on a first value associated with the set of pages and a second value associated with the partition.

Abstract: An apparatus can comprise a memory array comprising a plurality of strings of memory cells each comprising: a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block; and a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block. A controller is configured to determine a cumulative amount of read disturb stress experienced by the first erase block by monitoring read disturb stress experienced by the first erase block due to: read operations performed on the first erase block; read operations performed on the second erase block; and program verify operations performed on the second erase block. The controller can perform an action on the first erase block responsive to the cumulative amount of read disturb stress experienced by the first erase block meeting a criteria.

Abstract: An apparatus can comprise a memory array comprising a plurality of strings of memory cells. Each string of the plurality of strings can comprise: a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block; and a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block. A controller is coupled to the memory array and configured to: perform a programming operation on the first group of memory cells of the first erase block; monitor a quantity of programming and/or erase operations performed on the second group of memory cells subsequent to the programming of the first group of memory cells; and perform an action on the first erase block responsive to the quantity of programming and/or erase operations performed on the second group of memory cells meeting a criteria.

Abstract: A method includes forming at least a portion of a first superblock using a first subset of blocks from at least one memory die of a memory sub-system and forming at least a portion of a second superblock using a second subset of blocks from the at least one memory die of the memory sub-system.

Abstract: A current value for a reference voltage for a block family is determined. An amount of voltage shift for a memory page of the block family is determined based on the current value for the reference voltage and a prior value for the reference voltage. The block family is associated with a first voltage bin or a second voltage bin based on the determined amount of voltage shift. The first voltage bin is associated with a first voltage offset and the second voltage bin is associated with a second voltage offset.

Abstract: Methods, systems, and devices for determining offsets for memory read operations are described. In response to a threshold quantity of pages failing initial reads but being successfully read using a same reference adjustment during re-reads, the offset responsible for the adjustment may be used as a first-applied offset for subsequent re-reads or a baseline offset for subsequent initial reads. After the initial reads begin using the reference adjustment, if a threshold quantity of pages fail initial reads, the offset used for the initial read may be adjusted to be the offset used to perform the successful re-reads. If an updated offset to use a baseline is not identified, the baseline offset may be cleared so the original reference may again be used without adjustment for initial reads.

Abstract: An example apparatus includes a media management superblock component configured to determine that a quantity of blocks of a superblock of a non-volatile memory array are bad blocks; compare the quantity of bad blocks to a bad block criteria; and write host data to the superblock with the quantity of bad blocks in response to the quantity of bad blocks meeting the bad block criteria. The use of the superblock with a particular quantity of bad block minimizes yield loss for non-use of partial superblocks.

Abstract: Methods, systems, and apparatuses related to source address memory management are described. For example, a controller can be coupled to a memory device to select a source block, a destination block, and a metadata block. The controller can store metadata indicative of an address of the source block in the metadata block. The controller can perform a memory management operation to transfer data from the source block to the destination block.

Abstract: Methods, systems, and devices for adaptive block mapping are described. In some examples, a first superblock and a second superblock may be established across one or more dice of a memory device. The superblocks may each include one or more blocks from a plurality of planes of a memory die. In some examples, the second superblock may include at least one bad block (e.g., defective block) in addition to one or more good blocks (e.g., non-defective blocks). The memory device may receive a command for writing data in a first mode and may write a first subset of the data to the first superblock in the first mode, a second subset of the data to the second superblock in the first mode, and one or more blocks associated with the second superblock in a second mode. Additionally or alternatively, the memory device may receive a second command for writing data in the second mode and may write the data to the first superblock in the first mode.

Abstract: A system can include a memory device with multiple management units, each management unit made up of multiple blocks, and a processing device, operatively coupled with the memory device, to perform various operations including identifying, among the management units, some complete management units and some incomplete management units, as well as performing one type of operation using one or more complete management units. The operations can also include performing another type of operation using one or more incomplete management units where this other type of operation include writing, to one or more incomplete management units, metadata associated with the data stored in complete management units.

Abstract: A variety of applications can include apparatus and/or methods to preemptively detect defect prone memory blocks in a memory device and handle these memory blocks before they fail and trigger a data loss event. Metrics based on memory operations can be used to facilitate the examination of the memory blocks. One or more metrics associated with a memory operation on a block of memory can be tracked and a Z-score for each metric can be generated. In response to a comparison of a Z-score for a metric to a Z-score threshold for the metric, operations can be performed to control possible retirement of the memory block beginning with the comparison. Additional apparatus, systems, and methods are disclosed.

Abstract: A parity generation operation based on a set of multiple planes of host data is executed to generate a set of multi-page parity data. The set of multi-page parity data is stored in a cache memory of a memory device. A data recovery operation is performed based on the set of multi-page parity data.

Abstract: Devices and techniques are disclosed herein for more efficiently performing random write operation for a memory device. In an example, a method of operating a flash memory device can include receiving a write request at a flash memory device from a host, the write request including a first logical block address and write data, saving the write data to a location of the flash memory device having a first physical address, operating the flash memory device in a first mode when an amount of write data associated with the write request is above a threshold, operating the flash memory device in a second mode when an amount of write data is below the threshold, and comparing the amount of write data to the threshold.

Abstract: A system includes a memory device having multiple dice and a processing device operatively coupled to the memory device. The processing device receives a memory operation to program a set of pages of data across at least a subset of the plurality of dice. The processing device partitions the set of pages into a set of partitions and associates a first partition of the set of partitions with a first block family. The processing device assigns the first block family to a first threshold voltage offset bin and stores, in a metadata table, at least one bit to indicate that the set of pages is partitioned.

Abstract: Provided is a multifunctional lithography device, including: a vacuum substrate-carrying stage configured to place a substrate and adsorb the substrate on the vacuum substrate-carrying stage by controlling an airflow, so as to control a gap between the substrate and the mask plate; a mask frame arranged above the vacuum substrate-carrying stage and configured to fix the mask plate; a substrate-carrying stage motion system arranged below the vacuum substrate-carrying stage and configured to adjust a position of the vacuum substrate-carrying stage, so that a distance between the substrate and the mask plate satisfies a preset condition; an ultraviolet light source system arranged above the mask plate and configured to generate an ultraviolet light for lithography; and a three-axis alignment optical path system configured to align the ultraviolet light with the mask plate.

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including performing, on data residing in a block of the memory device, an error-handling operation of a plurality of error-handling operations, wherein an order of the plurality of error-handling operations is based on a voltage offset bin associated with the block, wherein the voltage offset bin defines a set of threshold voltage offsets to be applied to a base voltage read level during read operations; and responsive to determining that the error-handling operation has failed to recover the data, adjusting the order of the plurality of error-handling operations.

Abstract: A method includes receiving a command to write data to a memory device and writing the data to a first memory tier of the memory device. The first memory tier of the memory device is a dynamic memory tier that utilizes single level cells (SLCs), multi-level cells (MLCs), and triple level cells (TLCs). The method further includes migrating the data from the first memory tier of the memory device to a second memory tier of the memory device. The second memory tier of the memory device is a static memory tier that utilizes quad level cells (QLCs).

Abstract: A system can include a memory device, and a processing device, operatively coupled with the memory device, to perform operations of writing a first portion of data to one or more complete translation units of the memory device using a first number of logical levels per memory cell and writing a second portion of the data to one or more incomplete translation units of the memory device using the first number of logical levels per memory cell. The operations can also include writing a third portion of the data to one or more complete translation units of the memory device using a second number of logical levels per memory cell that exceeds the first number of logical levels per memory cell.

Abstract: Methods, systems, and devices for adaptive block mapping are described. In some examples, a first superblock and a second superblock may be established across one or more dice of a memory device. The superblocks may each include one or more blocks from a plurality of planes of a memory die. In some examples, the second superblock may include at least one bad block (e.g., defective block) in addition to one or more good blocks (e.g., non-defective blocks). The memory device may receive a command for writing data in a first mode and may write a first subset of the data to the first superblock in the first mode, a second subset of the data to the second superblock in the first mode, and one or more blocks associated with the second superblock in a second mode. Additionally or alternatively, the memory device may receive a second command for writing data in the second mode and may write the data to the first superblock in the first mode.

Abstract: A voltage shift for memory cells of a block family at a memory device is measured. The block family is associated with a first voltage offset. An adjusted amount of voltage shift is determined for the memory cells based on the measured voltage shift and a temporary voltage shift offset associated with a difference between a current temperature and a prior temperature for the memory device. The block family is associated with a second voltage offset in view of the adjusted voltage shift.