Patents by Inventor Xiangning Wang
Xiangning Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240133804Abstract: An on-line multi-component gas analysis system based on a spectral absorption technology includes a housing, wherein the housing includes an air inlet hole and an air outlet hole which are respectively connected with an air inlet pipe and an air outlet pipe, and the housing includes a dust removal and dehumidification device, a micro vacuum pump, an electronic flowmeter, and a plurality of different gas sensors; the dust removal and dehumidification device, which is configured to perform dust removal and dehumidification treatment on a gas entering from the air inlet hole; the micro vacuum pump, one end of which being connected with the dust removal and dehumidification device through a pipeline, and the other end of which being connected with the electronic flowmeter; and the plurality of different gas sensors. The disclosure includes an analysis method based on the on-line multi-component gas analysis system based on a spectral absorption technology.Type: ApplicationFiled: December 19, 2023Publication date: April 25, 2024Inventors: Yuntao LIANG, Fuchao Tian, Shuanglin Song, Xiangning Meng, Yong Sun, Rui Zhou, Jincheng Wang, Zhongyu Zheng
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Patent number: 11950419Abstract: A three-dimensional (3D) memory device is provided. In an example, the 3D memory device includes a staircase and a plurality of groups of support structures through the staircase. The plurality of groups of support structures are arranged in a first direction, and each of the groups of support structures comprises three support structures, wherein projections of the three support structures form a triangular shape in a plane parallel to the first direction.Type: GrantFiled: April 15, 2021Date of Patent: April 2, 2024Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Zongke Xu, Bin Yuan, Xiangning Wang, Qiangwei Zhang
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Patent number: 11950418Abstract: Embodiments of a three-dimensional (3D) memory device and fabrication methods thereof are disclosed. In an example, a method for forming a 3D memory device includes the following operations. A dielectric stack is formed to have interleaved sacrificial layers and dielectric layers. A stair is formed in the dielectric stack. The stair includes one or more sacrificial layers of the sacrificial layers and one or more dielectric layers of the dielectric layers. The stair exposes one of the sacrificial layers on a top surface and the one or more sacrificial layers on a side surface. An insulating portion is formed to cover the side surface of the stair to cover the one or more sacrificial layers. A sacrificial portion is formed to cover the top surface of the stair. The sacrificial portion is in contact with the one of sacrificial layers. The one or more sacrificial layers and the sacrificial portion are replaced with one or more conductor layers.Type: GrantFiled: March 30, 2021Date of Patent: April 2, 2024Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Xinxin Liu, Jingjing Geng, Zhu Yang, Chen Zuo, Xiangning Wang
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Publication number: 20230301106Abstract: Embodiments of three-dimensional (3D) memory devices are disclosed. In an example, a 3D memory device includes a semiconductor layer, a memory stack over the semiconductor layer, first channel structures each extending vertically through the memory stack in an edge region, and an isolation structure. The memory stack includes a plurality of interleaved conductive layers and dielectric layers. At least one of conductive layers toward the semiconductor layer is a source select gate line (SSG). The isolation structure extends vertically through the SSG and into the semiconductor layer. The memory stack includes a core array region, a staircase region, and the edge region being laterally between the core array region and the staircase region. At least one of the first channel structures extends through the isolation structure and is separated from the SSG through the isolation structure.Type: ApplicationFiled: May 25, 2023Publication date: September 21, 2023Inventors: Zhen Guo, Jingjing Geng, Bin Yuan, Jiajia Wu, Xiangning Wang, Zhu Yang, Chen Zuo
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Patent number: 11711921Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack on the substrate, a plurality of channel structures each extending vertically through the memory stack, an isolation structure, and an alignment mark. The memory stack includes a plurality of interleaved conductive layers and dielectric layers. An outmost one of the conductive layers toward the substrate is a source select gate line (SSG). The isolation structure extends vertically into the substrate and surrounds at least one of the channel structures in a plan view to separate the SSG and the at least one channel structure. The alignment mark extends vertically into the substrate and is coplanar with the isolation structure.Type: GrantFiled: October 29, 2020Date of Patent: July 25, 2023Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Zhen Guo, Jingjing Geng, Bin Yuan, Jiajia Wu, Xiangning Wang, Zhu Yang, Chen Zuo
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Publication number: 20230148055Abstract: A method of fabricating a three-dimensional memory includes forming a laminated structure including stacked dummy gate layers and interlayer insulation layers on one side of a substrate. The respective adjacent dummy gate layers and interlayer insulation layers form staircase stairs. At least a part of the interlayer insulation layer of each of the staircase stairs is exposed. The method also includes forming a buffer layer covering the staircase stairs. The method further includes removing a part of the buffer layer covering the sidewalls of the staircase stairs to form spacing grooves. The method further includes forming a dielectric layer that fills the spacing grooves and covers the staircase stairs. The method further includes forming a contact hole penetrating through the dielectric layer and the buffer layer and extending to the dummy gate layer farthest from the substrate.Type: ApplicationFiled: December 27, 2022Publication date: May 11, 2023Inventors: Zhen Guo, Bin Yuan, Zongke Xu, Jiajia Wu, Beibei Li, Xiangning Wang, Zhu Yang, Qiangwei Zhang
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Publication number: 20230095343Abstract: Embodiments of a three-dimensional (3D) memory device and fabrication methods thereof are disclosed. In an example, a 3D memory device includes a memory stack having a plurality of stairs. Each stair may include interleaved one or more conductor layers and one or more dielectric layers. Each of the stairs includes one of the conductor layers on a top surface of the stair, the one of the conductor layers having (i) a bottom portion in contact with one of the dielectric layers, and (ii) a top portion exposed by the memory stack and in contact with the bottom portion. A lateral dimension of the top portion may be less than a lateral dimension of the bottom portion. An end of the top portion that may be facing away from the memory stack laterally exceeds the bottom portion by a distance.Type: ApplicationFiled: December 8, 2022Publication date: March 30, 2023Inventors: Xinxin Liu, Jingjing Geng, Zhu Yang, Chen Zuo, Xiangning Wang
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Patent number: 11552097Abstract: Embodiments of a three-dimensional (3D) memory device and fabrication methods thereof are disclosed. In an example, a 3D memory device includes a memory stack having a plurality of stairs. Each stair may include interleaved one or more conductor layers and one or more dielectric layers. Each of the stairs includes one of the conductor layers on a top surface of the stair, the one of the conductor layers having (i) a bottom portion in contact with one of the dielectric layers, and (ii) a top portion exposed by the memory stack and in contact with the bottom portion. A lateral dimension of the top portion may be less than a lateral dimension of the bottom portion. An end of the top portion that may be facing away from the memory stack laterally exceeds the bottom portion by a distance.Type: GrantFiled: December 26, 2019Date of Patent: January 10, 2023Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Xinxin Liu, Jingjing Geng, Zhu Yang, Chen Zuo, Xiangning Wang
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Publication number: 20220293627Abstract: A three-dimensional (3D) memory device is provided. In an example, the 3D memory device includes a staircase and a plurality of groups of support structures through the staircase. The plurality of groups of support structures are arranged in a first direction, and each of the groups of support structures comprises three support structures, wherein projections of the three support structures form a triangular shape in a plane parallel to the first direction.Type: ApplicationFiled: April 15, 2021Publication date: September 15, 2022Inventors: Zongke Xu, Bin Yuan, Xiangning Wang, Qiangwei Zhang
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Publication number: 20220231043Abstract: Aspects of the disclosure provide semiconductor devices. For example, a semiconductor device includes a substrate having a first region and a second region along a first direction that is parallel to a main surface of the substrate. Then, the semiconductor device includes a memory stack that includes a first stack of alternating gate layers and insulating layers and a second stack of alternating gate layers and insulating layers along a second direction that is perpendicular to the main surface of the substrate. Further, the semiconductor device includes a joint insulating layer in the second region and a third stack of alternating gate layers and insulating layers in the first region between the first stack of alternating gate layers and insulating layers and the second stack of alternating gate layers and insulating layers.Type: ApplicationFiled: March 26, 2021Publication date: July 21, 2022Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Qiangwei ZHANG, Jingjing GENG, Bin YUAN, Xiangning WANG, Chen ZUO, Zhu YANG, Liming CHENG, Zhen GUO
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Publication number: 20220223469Abstract: The present disclosure provides a method for forming a three-dimensional (3D) memory. In an example, the method includes forming a stack structure having interleaved a plurality of stack first layers and a plurality of stack second layers, forming a stair in the stack structure, the stair having one of the stack first layers on a top surface, and forming a layer of sacrificial material having a first portion over a side surface of the stair and a second portion over the top surface of the stair. The method also includes partially removing the first portion of the layer of sacrificial material using an anisotropic etching process and removing a remaining portion of the first portion of the layer of sacrificial material using an isotropic etching process.Type: ApplicationFiled: January 29, 2021Publication date: July 14, 2022Inventors: Xiangning Wang, Bin Yuan, Chen Zuo, Zhu Yang, Zongke Xu
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Publication number: 20220181349Abstract: Aspects of the disclosure provide methods for fabricating semiconductor devices. In some examples, a method for fabricating a semiconductor device includes forming a stack of layers having a first region and a second region. The stack of layers includes at least a first layer. The method then forms a hard mask layer on the stack of layers in the first region. Then, the method includes patterning the stack of layers in the second region of the semiconductor device. The patterning of the stack of layers in the second region removes a portion of the stack of layers in the second region, and exposes a side of the stack of layers. The method further includes covering at least the side of the stack of layers with a second layer that has a lower remove rate than the first layer, and then the method includes removing the hard mask layer.Type: ApplicationFiled: March 26, 2021Publication date: June 9, 2022Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Bin YUAN, Zhu YANG, Xiangning WANG, Chen ZUO, Jingjing GENG, Zhen GUO, Zongke XU, Qiangwei ZHANG
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Publication number: 20220085181Abstract: Aspects of the disclosure provide a method for fabricating a semiconductor device having an first stack of alternating insulating layers and sacrificial word line layers arranged over a substrate, the first stack including a core region and a staircase region. The method can include forming a first dielectric trench in the core region of the first stack, forming a second dielectric trench that is adjacent to and connected with the first dielectric trench in the staircase region of the first stack, and forming dummy channel structures extending through the first stack where the dummy channel structures are spaced apart from the second dielectric trench.Type: ApplicationFiled: December 23, 2020Publication date: March 17, 2022Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Hang YIN, Zhipeng WU, Kai HAN, Lu ZHANG, Pan WANG, Xiangning WANG, Hui ZHANG, Jingjing GENG, Meng XIAO
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Publication number: 20220077181Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack on the substrate, a plurality of channel structures each extending vertically through the memory stack, an isolation structure, and an alignment mark. The memory stack includes a plurality of interleaved conductive layers and dielectric layers. An outmost one of the conductive layers toward the substrate is a source select gate line (SSG). The isolation structure extends vertically into the substrate and surrounds at least one of the channel structures in a plan view to separate the SSG and the at least one channel structure. The alignment mark extends vertically into the substrate and is coplanar with the isolation structure.Type: ApplicationFiled: October 29, 2020Publication date: March 10, 2022Inventors: Zhen Guo, Jingjing Geng, Bin Yuan, Jiajia Wu, Xiangning Wang, Zhu Yang, Chen Zuo
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Publication number: 20210249438Abstract: Embodiments of a three-dimensional (3D) memory device and fabrication methods thereof are disclosed. In an example, a method for forming a 3D memory device includes the following operations. A dielectric stack is formed to have interleaved sacrificial layers and dielectric layers. A stair is formed in the dielectric stack. The stair includes one or more sacrificial layers of the sacrificial layers and one or more dielectric layers of the dielectric layers. The stair exposes one of the sacrificial layers on a top surface and the one or more sacrificial layers on a side surface. An insulating portion is formed to cover the side surface of the stair to cover the one or more sacrificial layers. A sacrificial portion is formed to cover the top surface of the stair. The sacrificial portion is in contact with the one of sacrificial layers. The one or more sacrificial layers and the sacrificial portion are replaced with one or more conductor layers.Type: ApplicationFiled: March 30, 2021Publication date: August 12, 2021Inventors: Xinxin Liu, Jingjing Geng, Zhu Yang, Chen Zuo, Xiangning Wang
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Publication number: 20210134830Abstract: Embodiments of a three-dimensional (3D) memory device and fabrication methods thereof are disclosed. In an example, a 3D memory device includes a memory stack having a plurality of stairs. Each stair may include interleaved one or more conductor layers and one or more dielectric layers. Each of the stairs includes one of the conductor layers on a top surface of the stair, the one of the conductor layers having (i) a bottom portion in contact with one of the dielectric layers, and (ii) a top portion exposed by the memory stack and in contact with the bottom portion. A lateral dimension of the top portion may be less than a lateral dimension of the bottom portion. An end of the top portion that may be facing away from the memory stack laterally exceeds the bottom portion by a distance.Type: ApplicationFiled: December 26, 2019Publication date: May 6, 2021Inventors: Xinxin Liu, Jingjing Geng, Zhu Yang, Chen Zuo, Xiangning Wang