Abstract: A Platform Environment Control Interface (PECI) signal interconnection method and system for a server, a computer device and a readable storage medium are provided. The method includes: acquiring a partition mode of the server; sending a corresponding first control signal and a corresponding second control signal to each computing node according to the partition mode; controlling a channel selection of a first switch on the corresponding computing node by the corresponding first control signal and controlling a channel selection of a second switch on the corresponding computing node by the corresponding second control signal; and transmitting PECI signals of the corresponding computing node through channels connected by the first switch and channels connected by the second switch. According to the described solution, interconnection routing of the PECI signals in a single-partition mode and a dual-partition mode may be achieved by using only one backplate.

Abstract: An open compute project (OCP) adapter card and a computer device are disclosed. The adapter card includes an OCP connector, a controller, a selector, and a motherboard connector. The OCP connector is configured to connect to an OCP network interface card (NIC). The controller is configured for bandwidth allocation, in-situ control and power-on/off control of the OCP NIC. The selector gates a single-homed host or a dual-homed host based on working mode configuration information stored in the controller. The motherboard connector is configured to connect to a motherboard device.

Abstract: The multi-path server comprises four circuits. Each circuit comprises a PCH, an extended module, a switch module, and a CPU. An extended module in the first circuit is connected to a switch module in the second circuit, a switch module in the third circuit, and a switch module in the fourth circuit. An extended module in the third circuit is connected to a switch module in the fourth circuit. A switch module performs switching action according to a target partition instruction, and a PCH performs in-place action according to the target partition instruction, such that each said circuit forms a target partition, and PMSYNC signals are interconnected in the target partition. A multi-path server signal interconnection system is also provided.

Abstract: A Platform Environment Control Interface (PECI) signal interconnection method and system for a server, a computer device and a readable storage medium are provided. The method includes: acquiring a partition mode of the server (S1); sending a corresponding first control signal and a corresponding second control signal to each computing node according to the partition mode (S2); controlling a channel selection of a first switch on the corresponding computing node by the corresponding first control signal and controlling a channel selection of a second switch on the corresponding computing node by the corresponding second control signal (S3); and transmitting PECI signals of the corresponding computing node through channels connected by the first switch and channels connected by the second switch (S4). According to the described solution, interconnection routing of the PECI signals in a single-partition mode and a dual-partition mode may be achieved by using only one backplate.

Abstract: An open compute project (OCP) adapter card and a computer device are disclosed. The adapter card includes an OCP connector, a controller, a selector, and a motherboard connector. The OCP connector is configured to connect to an OCP network interface card (NIC). The controller is configured for bandwidth allocation, in-situ control and power-on/off control of the OCP NIC. The selector gates a single-homed host or a dual-homed host based on working mode configuration information stored in the controller. The motherboard connector is configured to connect to a motherboard device.

Abstract: A method of forming nickel self-aligned silicide (Ni-salicide) is disclosed, the method including the following steps in the sequence set forth: providing a substrate; forming a gate on the substrate and forming a SiGe source and a SiGe drain beneath a surface of the substrate; growing a silicon epitaxial layer over the SiGe source and the SiGe drain; amorphizing the silicon epitaxial layer; depositing a Ni—Pt layer over the amorphized silicon epitaxial layer; performing a first rapid thermal anneal process to cause Ni—Pt alloy and the amorphized silicon epitaxial layer to react; removing the unreacted Ni—Pt alloy by wet etching; and performing a second rapid thermal anneal process to form a Ni-salicide.