Patents by Inventor XIAO-GUO ZHENG

XIAO-GUO ZHENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230260532
    Abstract: A method for adjusting audio frequency includes steps of: obtaining initial frequency and temporary data storage of audio data input to a buffering unit; performing a first adjustment procedure on initial frequency to obtain a first variation of temporary data storage corresponding to a first change of initial frequency; calculating a first frequency correction amount according to first variation and a first period of first adjustment procedure; adjusting initial frequency into first frequency according to first frequency correction amount; inputting first frequency into buffering unit; performing a second adjustment procedure on first frequency to obtain a second variation of temporary data storage corresponding to a second change of first frequency; calculating a second frequency correction amount according to second variation and a second period of second adjustment procedure, which first period is less than second period; and adjusting first frequency into target frequency according to second frequency co
    Type: Application
    Filed: November 17, 2022
    Publication date: August 17, 2023
    Inventors: Liang ZHANG, Xiao-Guo ZHENG
  • Patent number: 11275126
    Abstract: A test system includes a transmitter, capacitor, and receiver. The transmitter includes: an output circuit coupled to the receiver via the capacitor; a transmitting circuit transmitting a predetermined signal to a pad of the output circuit during a first test; a signal generator outputting a first signal and second signal to the pad during a first process and second process of a second test; and a comparator comparing the pad's signal with a reference signal in the first process and second process to determine whether the second test passes. The receiver includes: an input circuit coupled to the transmitter via the capacitor; a switch coupled between the input circuit and a receiving circuit to be conducting in the first test and second process and nonconducting in the first process; and the receiving circuit determining whether the first test passes according to the predetermined signal and assisting the capacitor in discharging.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: March 15, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Feng-Cheng Chang, Xiao-Guo Zheng, Wei-Xiong He
  • Publication number: 20210011091
    Abstract: A test system includes a transmitter, capacitor, and receiver. The transmitter includes: an output circuit coupled to the receiver via the capacitor; a transmitting circuit transmitting a predetermined signal to a pad of the output circuit during a first test; a signal generator outputting a first signal and second signal to the pad during a first process and second process of a second test; and a comparator comparing the pad's signal with a reference signal in the first process and second process to determine whether the second test passes. The receiver includes: an input circuit coupled to the transmitter via the capacitor; a switch coupled between the input circuit and a receiving circuit to be conducting in the first test and second process and nonconducting in the first process; and the receiving circuit determining whether the first test passes according to the predetermined signal and assisting the capacitor in discharging.
    Type: Application
    Filed: June 25, 2020
    Publication date: January 14, 2021
    Inventors: FENG-CHENG CHANG, XIAO-GUO ZHENG, WEI-XIONG HE
  • Patent number: 9686105
    Abstract: The present disclosure provides a crystal-less clock and data recovery (CDR) circuit and a frequency detection method thereof. The CDR circuit includes a clock generator and a frequency detection module. The clock generator is operable to generate a clock signal. The frequency detection module coupled to the clock generator is configured for outputting a control signal to the clock generator to increase or decrease the frequency of the clock signal according to a data signal received and a transition density.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: June 20, 2017
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Feng-Cheng Chang, Xiao-Guo Zheng
  • Publication number: 20160211964
    Abstract: The present disclosure provides a crystal-less clock and data recovery (CDR) circuit and a frequency detection method thereof. The CDR circuit includes a clock generator and a frequency detection module. The clock generator is operable to generate a clock signal. The frequency detection module coupled to the clock generator is configured for outputting a control signal to the clock generator to increase or decrease the frequency of the clock signal according to a data signal received and a transition density.
    Type: Application
    Filed: January 12, 2016
    Publication date: July 21, 2016
    Inventors: FENG-CHENG CHANG, XIAO-GUO ZHENG