Abstract: The present disclosure provides a complex programmable logic device (CPLD) and a communication method. The CPLD includes a data transmission module, a first in first out (FIFO) memory, and an I2C slave. The data transmission module obtains a first signal of the server, the FIFO memory obtains the first signal transmitted by the data transmission module, and the I2C slave obtains the first signal transmitted by the FIFO memory, so that the baseboard management controller (BMC) reads the first signal from the I2C slave through an I2C bus.

Abstract: A system for maintaining the operation of a cooling fan for a server if that function of a baseboard management controller (BMC) of the server should fail includes the BMC and a control module. The control module is electrically connected to the BMC and the fan, and the control module receives a first signal outputted by the BMC in a cycle and determines the state of the BMC depending on whether the first signal includes a change in level or fails to include a change in level. When an abnormal state of the BMC is determined, the control module outputs a preset pulse width modulation (PWM) signal to the fan to maintain operation of the fan. The present disclosure also provides a fan control method.

Abstract: A system for debugging server startups incorporated in a method applied in a server includes voltage regulators, a complex programmable logic device (CPLD), a transmitting device, and a display device. The voltage regulators transmit power-on signals required when the server is started. The CPLD receives the power-on signals, collects a second signal from the power on signals, and converts the second signals into a second data. The transmitting device receives the second data and parses the second data into a third data. The displaying device receives the third data and displays power-on signals that do not meet required standard during startup of server, according to the third data.

Abstract: A method of automatic identification of PCIe configuration of a server and preventing operation if each slimline connector connected with a PCIe device is found connected to an incorrect slot of a mother board utilizes a combination of first and second signals of two null interfaces of the first connector as that ID signal and a combination of third and fourth signals of the two interfaces of a second connector as that ID signal. The CPLD receiving the ID signals detects whether the first and second slimline connectors are in their specified and correct slots. Powering on of computer is not permitted if incorrect connection is found, and a warning prompt is generated. A PCIe channel width for each slimline is automatically configured if no incorrect connection is found. A server applying the method is also disclosed.

Abstract: A system for debugging server startups incorporated in a method applied in a server includes voltage regulators, a complex programmable logic device (CPLD), a transmitting device, and a display device. The voltage regulators transmit power-on signals required when the server is started. The CPLD receives the power-on signals, collects a second signal from the power on signals, and converts the second signals into a second data. The transmitting device receives the second data and parses the second data into a third data. The displaying device receives the third data and displays power-on signals that do not meet required standard during startup of server, according to the third data.

Abstract: A method for providing more than one function to pins of a programmable device used in a server system includes the programmable device and first and second devices. The programmable device is electrically connected to the first device and the second device. The programmable device includes a major logic communication device, a detection module, a storage module, and at least one multiplexing pin. The second device is powered on, sending an in-position signal to the detection module through the at least one multiplexing pin. The detection module transmits the in-position signal to the storage module. The major logic communication module communicates with the first device through the at least one multiplexing pin. A system applying the method are also disclosed.

Abstract: A method of automatic identification of PCIe configuration of a server and preventing operation if each slimline connector connected with a PCIe device is found connected to an incorrect slot of a mother board utilizes a combination of first and second signals of two null interfaces of the first connector as that ID signal and a combination of third and fourth signals of the two interfaces of a second connector as that ID signal. The CPLD receiving the ID signals detects whether the first and second slimline connectors are in their specified and correct slots. Powering on of computer is not permitted if incorrect connection is found, and a warning prompt is generated. A PCIe channel width for each slimline is automatically configured if no incorrect connection is found. A server applying the method is also disclosed.

Abstract: In a method and system for identifying addresses of slave devices, the system includes a main board, slave devices, and a power source. The main board is electrically connected to the slave devices and a delay unit is set in each slave device. An output terminal of the delay unit is electrically connected to the main board. The delay unit outputs a delay signal to the main board when first powered on, the main board receives the delay signal, computes a delay time of the delay signal, and by reference to a preset table identifies the slave device based on the specific delay time. Occupation of input and output I/O pins is reduced, a device for identifying addresses of slave devices is also disclosed.

Abstract: A method for processing data between host computer and CPLD provides a host computer, a circuit board comprising a UART unit, a pre-debugged hardware, and a CPLD. The UART unit communicates with the host computer via UART. The method further provides the CPLD coupled between the UART unit and the pre-debugged hardware and allows the CPLD to receive data from the host computer via the UART unit and to analyze the data. According to the method, the CPLD debugs the pre-debugged hardware according to the analyzed data and obtains a result of debugging. The CPLD outputs the result and allows the CPLD to transmit the result to the host computer via the UART unit. A system using the method is also provided.

Abstract: In a method and system for identifying addresses of slave devices, the system includes a main board, slave devices, and a power source. The main board is electrically connected to the slave devices and a delay unit is set in each slave device. An output terminal of the delay unit is electrically connected to the main board. The delay unit outputs a delay signal to the main board when first powered on, the main board receives the delay signal, computes a delay time of the delay signal, and by reference to a preset table identifies the slave device based on the specific delay time. Occupation of input and output I/O pins is reduced, a device for identifying addresses of slave devices is also disclosed.

Abstract: A method for providing more than one function to pins of a programmable device used in a server system includes the programmable device and first and second devices. The programmable device is electrically connected to the first device and the second device. The programmable device includes a major logic communication device, a detection module, a storage module, and at least one multiplexing pin. The second device is powered on, sending an in-position signal to the detection module through the at least one multiplexing pin. The detection module transmits the in-position signal to the storage module. The major logic communication module communicates with the first device through the at least one multiplexing pin. A system applying the method are also disclosed.

Abstract: A single-wire two-way communication circuit includes two chips and a data transmission line coupled between the two chips. Each chip includes a random access memory, a data control module, a data line control module, and a data line monitoring module. The random access memory stores data. The data control module obtains data of a first address from the random access memory and stores data of a second address received from the other chip into a second address of the random access memory. The data line control module sends the obtained data of the first address to the other chip through the data transmission line to perform a write operation. The data line monitoring module receives the data of the second address sent by the other chip through the data transmission line to perform a read operation.

Abstract: A debugging device includes a plurality of debug units, a UART port, and a processor. The debugging device is communicated with an electronic device through the UART port. The processor can receive debug signals from the terminal through the UART port, generate a plurality of debug controlling commands based on the debug signals, and send the plurality of debug controlling commands to the plurality of debug units, for controlling the plurality of debug units to debug the electronic device according to the plurality of debug controlling commands.

Abstract: A single-wire two-way communication circuit includes two chips and a data transmission line coupled between the two chips. Each chip includes a random access memory, a data control module, a data line control module, and a data line monitoring module. The random access memory stores data. The data control module obtains data of a first address from the random access memory and stores data of a second address received from the other chip into a second address of the random access memory. The data line control module sends the obtained data of the first address to the other chip through the data transmission line to perform a write operation. The data line monitoring module receives the data of the second address sent by the other chip through the data transmission line to perform a read operation.

Abstract: A method for processing data between host computer and CPLD provides a host computer, a circuit board comprising a UART unit, a pre-debugged hardware, and a CPLD. The UART unit communicates with the host computer via UART. The method further provides the CPLD coupled between the UART unit and the pre-debugged hardware and allows the CPLD to receive data from the host computer via the UART unit and to analyze the data. According to the method, the CPLD debugs the pre-debugged hardware according to the analyzed data and obtains a result of debugging. The CPLD outputs the result and allows the CPLD to transmit the result to the host computer via the UART unit. A system using the method is also provided.

Abstract: A debugging device includes a plurality of debug units, a UART port, and a processor. The debugging device is communicated with an electronic device through the UART port. The processor can receive debug signals from the terminal through the UART port, generate a plurality of debug controlling commands based on the debug signals, and send the plurality of debug controlling commands to the plurality of debug units, for controlling the plurality of debug units to debug the electronic device according to the plurality of debug controlling commands.

Abstract: A system and method for protecting firmware of baseboard management controller (BMC) includes a serial peripheral interface read only memory device (SPI ROM) and a logic controlling unit. The SPI ROM includes first and second blocks, the first block stores a main program, and the second block stores backup program. The logic controlling unit includes a protecting module, a determining module, and a controlling module. The protecting module write-protects the main program and the backup program of the SPI ROM. The determining module determines whether the main program of the first block is altered or damaged when the main program is obtained by the BMC. If so, the controlling module invokes the backup program from the second block, and writes the backup program to the first block. A firmware protecting method is also provided.

Abstract: A system and method for protecting firmware of baseboard management controller (BMC) includes a serial peripheral interface read only memory device (SPI ROM) and a logic controlling unit. The SPI ROM includes first and second blocks, the first block stores a main program, and the second block stores backup program. The logic controlling unit includes a protecting module, a determining module, and a controlling module. The protecting module write-protects the main program and the backup program of the SPI ROM. The determining module determines whether the main program of the first block is altered or damaged when the main program is obtained by the BMC. If so, the controlling module invokes the backup program from the second block, and writes the backup program to the first block. A firmware protecting method is also provided.

Abstract: A data communication system applied in an Inter-Integrated Circuit (I2C) bus serving more than one master device includes a first master device, a second master device, and a logic control unit. The logic control unit receives serial data line (SDA) signal and serial clock line (SCL) signal from the I2C bus of the first master device and of the second master device, and determines a priority between the first master device and the second master device, control of the I2C bus without prejudicing any current messaging is allocated accordingly. A data communication method is also provided.

Abstract: A data communication system applied in an Inter-Integrated Circuit (I2C) bus to enable functioning without a buffer or hub includes a complex programmable logic device (CPLD), a master device, and a plurality of slave devices. The CPLD detects changes in level of the SDA signal of the I2C bus between the master device and one of the slave devices, and determines a direction of an SDA signal as being from the I2C bus of the master device or from the I2C bus of the slave device.