Abstract: A multi-purpose digital damping device and application thereof is disclosed. The device comprises a mandrel, a movement disc disposed in a middle section of the mandrel, a first body and a second body rotationally connected to the mandrel, an inertia wheel rotationally connected coaxially to the mandrel, a pulse-width modulation circuit electrically connected to a coil. The first body and the second body are disposed respectively on each side of the movement disc and are merged by a seal ring to form a sealing cavity. A magnetic powder and the movement disc are both disposed in the sealing cavity. A coil frame for coil mounting is provided outside of the sealing cavity. The coil is mounted on the coil frame. A third body is provided for enclosing the coil on the coil frame. The third body is detachably connected respectively to the first body and the second body.

Abstract: Various embodiments disclose a method for operating a printer apparatus that includes a print head. The method includes causing a media hub to retract a media in a retract direction along a media path. Further, the method includes causing a first media sensor to generate a first signal during retraction of the media. Furthermore, the method includes monitoring the first signal to detect at least one of a leading edge or a trailing edge of a label of the plurality of labels. Upon detecting the at least one of the leading edge or the trailing edge of the label, causing the media hub to retract the media by at least a predetermined distance, wherein the predetermined distance is a distance between the print head and the first media sensor.

Abstract: A storage apparatus includes a controller and a storage medium. The storage medium includes a command decoder and a plurality of storage units. The controller is connected to the command decoder of the storage medium. The controller is configured to send a first processing command to the command decoder of the storage medium, where the first processing command includes first information and second information, the first information indicates a processing manner, and the second information indicates a data length of data to be processed.

Abstract: In a computer device, a memory sharing control device is deployed between a processor and a memory pool, and the processor accesses the memory pool via the memory sharing control device. Different processing units, such as processors or cores in processors, access one memory in the memory pool in different time periods, so that the memory is shared by a plurality of processing units, and utilization of memory resources is improved.

Abstract: Embodiments of this application disclose a storage device and a computer device, and belong to the field of computer technologies. The storage device includes a first PCM, a main memory, and a controller. The first PCM and the controller are packaged in a same chip. A latency of the first PCM is less than that of the main memory, and storage density of the main memory is greater than that of the first PCM. The controller is configured to store data in the first PCM and the main memory based on a read/write temperature of the data, where the first PCM is a cache of the main memory. According to embodiments of this application, a cache capacity of the storage device can be increased, and device costs can be reduced.

Abstract: Systems, apparatus and methods are provided for providing an error correction code (ECC) architecture with flexible memory mapping. An apparatus may include an error correction code (ECC) engine, a multi-channel interface for one or more non-volatile storage devices, a memory including a plurality of memory units, a storage containing a plurality of mapping entries to indicate allocation status of the plurality of memory units and a memory mapping manager. The plurality of memory units may be coupled to the ECC engine and the multi-channel interface. The memory mapping manager may be configured to control allocation of the plurality of memory units and set allocation status in the plurality of mapping entries.

Abstract: Systems, apparatus and methods are provided for providing an error correction code (ECC) architecture with flexible memory mapping. An apparatus may include an error correction code (ECC) engine, a multi-channel interface for one or more non-volatile storage devices, a memory including a plurality of memory units, a storage containing a plurality of mapping entries to indicate allocation status of the plurality of memory units and a memory mapping manager. The plurality of memory units may be coupled to the ECC engine and the multi-channel interface. The memory mapping manager may be configured to control allocation of the plurality of memory units and set allocation status in the plurality of mapping entries.

Abstract: Systems, apparatus and methods are provided for providing an error correction code (ECC) architecture with flexible memory mapping. An apparatus may include an error correction code (ECC) engine, a multi-channel interface for one or more non-volatile storage devices, a memory including a plurality of memory units, a storage containing a plurality of mapping entries to indicate allocation status of the plurality of memory units and a memory mapping manager. The plurality of memory units may be coupled to the ECC engine and the multi-channel interface. The memory mapping manager may be configured to control allocation of the plurality of memory units and set allocation status in the plurality of mapping entries.

Abstract: Systems, apparatus and methods are provided for providing an error correction code (ECC) architecture with flexible memory mapping. An apparatus may include an error correction code (ECC) engine, a multi-channel interface for one or more non-volatile storage devices, a memory including a plurality of memory units, a storage containing a plurality of mapping entries to indicate allocation status of the plurality of memory units and a memory mapping manager. The plurality of memory units may be coupled to the ECC engine and the multi-channel interface. The memory mapping manager may be configured to control allocation of the plurality of memory units and set allocation status in the plurality of mapping entries.

Abstract: Flow meters are disclosed that provide improved measurements of fluid flowing through fan coils. A flow meter includes a body that defines an inlet, an outlet, and a flow path extending along a longitudinal axis between the inlet and the outlet. The flow meter also includes transducers coupled to the body and exposed to the flow path defined by the body. The transducers are configured to transmit and receive a signal travelling through the flow path to measure a flow rate of fluid of the fan coil. The flow meter also includes one or more reflectors coupled to the body and exposed to the flow path defined by the body. Each of the one or more reflectors has a flat reflective surface that is exposed to the flow path and is configured to reflect the signal to relay the signal between the transducers.

Abstract: A data management apparatus, a data management method, and a data storage device are provided. The data management apparatus includes a management unit and a data migration unit. The management unit manages data transmission channels between two types of storage media with different transmission performance. Then, the data migration unit migrates data between the two types of storage media through the managed data transmission channels. In this way, the data management apparatus can directly migrate data between storage media with different transmission performance, and a CPU in a system does not need to perform processing such as instruction conversion and protocol conversion, so that a delay of performing the foregoing processing by the CPU can be shortened. In addition, because the CPU does not need to perform data migration, resource overheads of the CPU can be reduced.

Abstract: This application discloses a data processing method for a memory device, an apparatus, and a system, and relates to the field of data storage technologies, so that memory capacity expansion can be implemented, and the memory capacity expansion is not limited by an original quantity of DDR channels. The memory device includes a controller, a first memory, and a second memory, the controller separately communicates with a processor, the first memory, and the second memory, and read/write performance of the first memory is higher than read/write performance of the second memory. The method includes receiving an operation request of the processor, where the operation request includes a logical address, and accessing the first memory or the second memory based on the logical address.

Abstract: Systems, apparatus and methods are provided for providing an error correction code (ECC) architecture with flexible memory mapping. An apparatus may include an error correction code (ECC) engine, a multi-channel interface for one or more non-volatile storage devices, a memory including a plurality of memory units, a storage containing a plurality of mapping entries to indicate allocation status of the plurality of memory units and a memory mapping manager. The plurality of memory units may be coupled to the ECC engine and the multi-channel interface. The memory mapping manager may be configured to control allocation of the plurality of memory units and set allocation status in the plurality of mapping entries.

Abstract: Systems, apparatus and methods are provided for providing an error correction code (ECC) architecture with flexible memory mapping. An apparatus may include an error correction code (ECC) engine, a multi-channel interface for one or more non-volatile storage devices, a memory including a plurality of memory units, a storage containing a plurality of mapping entries to indicate allocation status of the plurality of memory units and a memory mapping manager. The plurality of memory units may be coupled to the ECC engine and the multi-channel interface. The memory mapping manager may be configured to control allocation of the plurality of memory units and set allocation status in the plurality of mapping entries.

Abstract: Systems, apparatus and methods are provided for providing an error correction code (ECC) architecture with flexible memory mapping. An apparatus may include an error correction code (ECC) engine, a multi-channel interface for one or more non-volatile storage devices, a memory including a plurality of memory units, a storage containing a plurality of mapping entries to indicate allocation status of the plurality of memory units and a memory mapping manager. The plurality of memory units may be coupled to the ECC engine and the multi-channel interface. The memory mapping manager may be configured to control allocation of the plurality of memory units and set allocation status in the plurality of mapping entries.

Abstract: Systems, apparatus and methods are provided for an error correction code (ECC) architecture with reduced decoding latency in error control. An apparatus may comprise control circuitry configured to receive a status report that a decoding task has failed, determine that a higher priority is needed for a re-decoding task, generate a NAND read task having a second priority level higher than a first priority level of the failed decoding task, and generate an ECC re-decoding task having the second priority level.

Abstract: An Internet Protocol Security tunnel maintenance method, apparatus, and system including a terminal device that negotiates with a VPN gateway based on a first IP address and according to the IKE protocol, and establishes an IPsec tunnel based on SAs obtained through negotiation; determines, the first IP address changes to a second IP address; sends a first request packet to the VPN gateway, where the first request packet carries the second IP address and a first tunnel identifier, where the first request packet is used to request to update a first SA record, and where the first SA record includes a correspondence between the SAs, the first IP address, and the first tunnel identifier; generates a second tunnel identifier based on the second IP address and a predefined algorithm; and replaces the first tunnel identifier in a second SA record with the second tunnel identifier.

Abstract: Systems, apparatus and methods are provided for an error correction code (ECC) architecture with reduced decoding latency in error control. An apparatus may comprise control circuitry configured to receive a status report that a decoding task has failed, determine that a higher priority is needed for a re-decoding task, generate a NAND read task having a second priority level higher than a first priority level of the failed decoding task, and generate an ECC re-decoding task having the second priority level.

Abstract: Systems, apparatus and methods are provided for providing an error correction code (ECC) architecture with flexible memory mapping. An apparatus may comprise an error correction code (ECC) engine, a multi-channel interface for one or more non-volatile storage devices, a memory comprising a plurality of memory units, a storage containing a plurality of mapping entries to indicate allocation status of the plurality of memory units and a memory mapping manager. The plurality of memory units may be coupled to the ECC engine and the multi-channel interface. The memory mapping manager may be configured to control allocation of the plurality of memory units and set allocation status in the plurality of mapping entries.

Abstract: Systems, apparatus and methods are provided for providing a flexible error correction code (ECC) architecture in a non-volatile storage system. A method for storing data may comprise generating a first error correction code (ECC) engine tag for a piece of data to be stored in a non-volatile storage device, routing the piece of data to a first type of ECC encoder of a plurality of types of ECC encoders according to the first ECC engine tag, encoding the piece of data using the first type of ECC encoder to generate ECC codeword(s) and transmitting the ECC codeword(s) to the non-volatile storage device for storage.