Abstract: A method for controlling a pipeline-based processor. The method includes determining a change in a workload. The method also includes activating or shutting down, by at least one controller circuit, one or more of the plurality of enhanced pipeline stages based on at least one corresponding enhanced stage priority level of the one or more of the plurality of enhanced pipeline stages and requirements for performance of the workload. The method additionally includes activating or shutting down, by the at least one controller circuit, one or more of the plurality of enhanced modules of the particular pipeline stage based on at least one corresponding priority level of the one or more of the plurality of enhanced modules of the particular pipeline stage and the requirements for the performance of the workload.

Abstract: A pipeline-based processor and method. The method includes partitioning a particular pipeline into one or more base pipeline stages and a plurality of enhanced pipeline stages, each enhanced pipeline stage configured to be either a shutdown enhanced pipeline stage or an activated enhanced pipeline stage. Each enhanced pipeline stage has an enhanced stage priority level. The method also includes configuring each enhanced pipeline stage to be activated or shut down based at least on the enhanced stage priority level. The method additionally includes partitioning a particular pipeline stage into at least one base module and a plurality of enhanced modules, each enhanced pipeline stage configured to be either a shutdown enhanced pipeline stage or an activated enhanced pipeline stage. Each enhanced module has a particular priority level. The method further includes configuring each enhanced module to be activated or shut down based at least on the particular priority level.

Abstract: The present invention discloses a pipeline-based central processing unit, wherein the pipeline is partitioned into base pipeline stages and enhanced pipeline stages according to functions, the base pipeline stages being activated all the while, and the enhanced pipeline stages being activated or shutdown according to requirements for performance of a workload. The present invention further discloses a pipeline-based central processing unit, wherein the pipeline is partitioned into base pipeline stages and enhanced pipeline stages according to functions, each pipeline stage being partitioned into a base module and at least one enhanced module, the base module being activated all the while, and the enhanced module being activated or shutdown according to requirements for performance of a workload.

Abstract: A method for controlling a pipeline-based processor. The method includes determining a change in a workload. The method also includes activating or shutting down, by at least one controller circuit, one or more of the plurality of enhanced pipeline stages based on at least one corresponding enhanced stage priority level of the one or more of the plurality of enhanced pipeline stages and requirements for performance of the workload. The method additionally includes activating or shutting down, by the at least one controller circuit, one or more of the plurality of enhanced modules of the particular pipeline stage based on at least one corresponding priority level of the one or more of the plurality of enhanced modules of the particular pipeline stage and the requirements for the performance of the workload.

Abstract: An apparatus for a hypervisor to obtain a faulting instruction, wherein the hypervisor runs between a physical machine including a central processing unit (CPU) and a virtual machine includes a content addressable memory (CAM); a special-purpose register (SPR) which is accessible by the hypervisor; and a control logic circuit with an input terminal connected to the CPU and an output terminal connected to the CAM, the input terminal receiving data from an instruction fetching (IF) stage and a write-back (WB) stage of a CPU instruction pipeline respectively, the output terminal causing instructions from the IF stage of the CPU instruction pipeline to be stored into the CAM and triggering the CAM to output a faulting instruction among the instructions stored therein to the SPR.

Abstract: Method and apparatus for managing a translation lookaside buffer (TLB) at hardware in a virtualization enabled system. According to embodiments of the present invention, a series of operations caused by TLB miss would not need intervening from the hypervisor. On the contrary, when a TLB miss occurs, the hardware directly issues an interrupt to a virtual machine. In this way, the TLB can be efficiently managed by means of a hardware-level auxiliary translation table. Therefore, system overheads can be greatly reduced and system performance can be improved. Methods and apparatuses associated with hardware, hypervisor, and virtual machine in a virtualization enabled system are disclosed, respectively.

Abstract: A pipeline-based processor and method. The method includes partitioning a particular pipeline into one or more base pipeline stages and a plurality of enhanced pipeline stages, each enhanced pipeline stage configured to be either a shutdown enhanced pipeline stage or an activated enhanced pipeline stage. Each enhanced pipeline stage has an enhanced stage priority level. The method also includes configuring each enhanced pipeline stage to be activated or shut down based at least on the enhanced stage priority level. The method additionally includes partitioning a particular pipeline stage into at least one base module and a plurality of enhanced modules, each enhanced pipeline stage configured to be either a shutdown enhanced pipeline stage or an activated enhanced pipeline stage. Each enhanced module has a particular priority level. The method further includes configuring each enhanced module to be activated or shut down based at least on the particular priority level.

Abstract: The present invention discloses a method of processing instructions in a pipeline-based central processing unit, wherein the pipeline is partitioned into base pipeline stages and enhanced pipeline stages according to functions, the base pipeline stages being activated all the while, and the enhanced pipeline stages being activated or shutdown according to requirements for performance of a workload. The present invention further discloses a method of processing instructions in a pipeline-based central processing unit, wherein the pipeline is partitioned into base pipeline stages and enhanced pipeline stages according to functions, each pipeline stage being partitioned into a base module and at least one enhanced module, the base module being activated all the while, and the enhanced module being activated or shutdown according to requirements for performance of a workload.

Abstract: An apparatus for a hypervisor to obtain a faulting instruction, wherein the hypervisor runs between a physical machine including a central processing unit (CPU) and a virtual machine includes a content addressable memory (CAM); a special-purpose register (SPR) which is accessible by the hypervisor; and a control logic circuit with an input terminal connected to the CPU and an output terminal connected to the CAM, the input terminal receiving data from an instruction fetching (IF) stage and a write-back (WB) stage of a CPU instruction pipeline respectively, the output terminal causing instructions from the IF stage of the CPU instruction pipeline to be stored into the CAM and triggering the CAM to output a faulting instruction among the instructions stored therein to the SPR.

Abstract: A data processing system and method are disclosed. The system comprises an instruction-fetch stage where an instruction is fetched and a specific instruction is input into decode stage; a decode stage where said specific instruction indicates that contents of a register in a register file are used as an index, and then, the register file pointed to by said index is accessed based on said index; an execution stage where an access result of said decode stage is received, and computations are implemented according to the access result of the decode stage.

Abstract: Method and apparatus for managing a translation lookaside buffer (TLB) at hardware in a virtualization enabled system. According to embodiments of the present invention, a series of operations caused by TLB miss would not need intervening from the hypervisor. On the contrary, when a TLB miss occurs, the hardware directly issues an interrupt to a virtual machine. In this way, the TLB can be efficiently managed by means of a hardware-level auxiliary translation table. Therefore, system overheads can be greatly reduced and system performance can be improved. Methods and apparatuses associated with hardware, hypervisor, and virtual machine in a virtualization enabled system are disclosed, respectively.

Abstract: A request control device, request control method, and a multiprocessor cooperation architecture. The request control device is connected to a request storage module and includes a comparing means and an identifier means. The comparing means is configured to determine if an incoming first queue unit corresponds to the same message with a queue unit that has existed in the request storage module. The identifier setting means is configured to set a save identifier of the queue unit that has existed in the request storage module to indicate not to save a state associated with the message if the first queue unit corresponds to the same message with the queue unit that has existed in the request storage module. According to the technical solution of the invention, the access to the memory caused by saving/loading the states is reduced and thereby increases the processing speed of the processor.

Abstract: This invention provides a request controlling apparatus, processor and method. The request controlling apparatus is connected to a request storage unit and includes: a queue unit storing flag recording region configured to record a storing flag corresponding to a queue unit in the request storage unit, a comparing means configured to judge whether a incoming first queue unit corresponds to a same message as an already existing queue unit, where the already existing queue unit is in the request storage unit and a flag setting means is configured to set the storing flag corresponding to the already existing queue unit in the queue unit storing flag recording region, to indicate that a message state related to the already existing queue unit will not be stored if the first queue unit corresponds to the same message as in the already existing queue unit.

Abstract: A processing unit coupled to a bus for accelerating data transmission and a method for accelerating data transmission. The present invention provides a streaming data transmission mode in which a plurality of data blocks are transmitted via one handshake. The present invention employs handshake save policy, when a processing unit sends a request comprising a plurality of data blocks on a bus, a cache or memory will perform address matching to judge whether there is any hit data block. If there is any hit data block, the cache or memory only needs to reply once and then start to continuously transmit the hit data blocks it possesses. Thus, a separate handshake for each data block is no longer needed.

Abstract: An apparatus and method for managing a translation look-aside buffer (TLB). The TLB is shared by a plurality of jobs. The method including the steps of: obtaining at least one attribute of each job of the plurality of jobs; assigning a priority level to each job according to at least one attribute of each job; and managing the related TLB entries of each job according to the priority level of each job. The present invention also provides an apparatus for managing TLB corresponding to the above method. The method and apparatus according to the present invention provide an efficient use of the shared TLB.

Abstract: A Simulator and a simulating method for running a guest program in a host are disclosed. The simulator includes: an initialization device configured for setting content of a hypervisor page table in the host, the hypervisor page table mapping a guest physical address space to a host physical address space. The simulator further includes a binary translation device configured for employing a program logical address to perform a memory access in code translation. The simulator also includes a miss handling device configured for updating a guest translation look-aside buffer by treating a miss in a host translation look-aside buffer caused by the execution of the translated code as a miss in the guest translation look-aside buffer, wherein the host translation look-aside buffer is configured to buffer entries for mapping addresses in a guest program logical address space to addresses in the guest physical address space.

Abstract: A method and system for compressing and encrypting data. The method includes: receiving original data; performing a first compression of said original data to obtain a first compression result; and encrypting only a literal portion in the first compression result to obtain an encrypted first compression result. Embodiments of the present invention improve the efficiency of the process of compression +encryption to a great extent by means of encrypting only the literal portion of the compression result.

Abstract: A method and system for compressing and encrypting data. The method includes: receiving original data; performing a first compression of the original data to obtain a first compression result; and encrypting only a literal portion in the first compression result to obtain an encrypted first compression result. Various embodiments improve the efficiency of the process of compression and encryption to a great extent by encrypting only the literal portion of the compression result.

Abstract: The present invention discloses a method of processing instructions in a pipeline-based central processing unit, wherein the pipeline is partitioned into base pipeline stages and enhanced pipeline stages according to functions, the base pipeline stages being activated all the while, and the enhanced pipeline stages being activated or shutdown according to requirements for performance of a workload. The present invention further discloses a method of processing instructions in a pipeline-based central processing unit, wherein the pipeline is partitioned into base pipeline stages and enhanced pipeline stages according to functions, each pipeline stage being partitioned into a base module and at least one enhanced module, the base module being activated all the while, and the enhanced module being activated or shutdown according to requirements for performance of a workload.

Abstract: A data processing system and method are disclosed. The system comprises an instruction-fetch stage where an instruction is fetched and a specific instruction is input into decode stage; a decode stage where said specific instruction indicates that contents of a register in a register file are used as an index, and then, the register file pointed to by said index is accessed based on said index; an execution stage where an access result of said decode stage is received, and computations are implemented according to the access result of the decode stage.