Abstract: A high electron mobility transistor (HEMT) device comprising a substrate, a plurality of semiconductor layers provided on the substrate, and a source terminal, a drain terminal and at least one gate terminal provided on the plurality of semiconductor layers. The HEMT also includes a metal ring formed on the plurality of semiconductor layers around the source terminal, the drain terminal and the at least one gate terminal, where the metal ring operates to shift the pinch-off voltage of the device. In one embodiment, the metal ring includes an ohmic portion and an electrode portion, where both the ohmic portion and the electrode portion include a lower titanium layer, a middle platinum layer and an upper gold layer.

Abstract: A method for fabricating a double-recess gate structure for an FET device that includes providing a semiconductor wafer having a plurality of semiconductor layers and depositing an EBL resist layer on the wafer. The method also includes patterning the EBL resist layer to form an opening in the EBL resist layer and performing a first wet etch to form a first recess in the wafer. The method further includes depositing a dielectric layer over the EBL resist layer and into the first recess and performing a dry etch to remove a portion of the dielectric layer in the first recess. The method also includes performing a second wet etch through the opening in the dielectric layer to form a second recess, and depositing a gate metal layer in the first and second recesses and in the opening in the EBL resist layer to form a gate terminal.

Abstract: An integrated circuit comprising a substrate including a top-side surface and a backside surface and a plurality of circuit components fabricated on the top-side surface of the substrate. The circuit includes a plurality of electrically conductive vias extending into the substrate from the backside surface of the substrate. Some of the plurality of vias are through vias that extend completely through the substrate and make electrical contact with a circuit component on the top-side surface of the substrate and some of the plurality of vias are part-way through vias that extend only part-way through the substrate and are positioned directly opposite to a circuit component on the top-side surface of the substrate, where the part-way through vias extend at least half-way through the substrate. The number of part-way through vias is determined based on the number of part-way through vias that are necessary to suppress substrate modes in the substrate.

Abstract: In a method of forming a semiconductor device on a semiconductor substrate (100), a photoresist layer (102) is deposited on the semiconductor substrate; a window (106) is formed in the photoresist layer (102) by electron beam lithography; a conformal layer (108) is deposited on the photoresist layer (102) and in the window (106); and substantially all of the conformal layer (108) is selectively removed from the photoresist layer (102) and a bottom portion of the window to form dielectric sidewalls (110) in the window (106).

Abstract: In a method of forming a semiconductor device on a semiconductor substrate (100), a photoresist layer (102) is deposited on the semiconductor substrate; a window (106) is formed in the photoresist layer (102) by electron beam lithography; a conformal layer (108) is deposited on the photoresist layer (102) and in the window (106); and substantially all of the conformal layer (108) is selectively removed from the photoresist layer (102) and a bottom portion of the window to form dielectric sidewalls (110) in the window (106).

Abstract: A semiconductor device with ohmic contact is provided with a method of making the same. In one embodiment, a method is provided for fabricating a semiconductor device. The method comprises providing a semiconductor structure with a N-type doped semiconductor contact layer, forming a platinum contact portion over the N-type doped semiconductor contact layer, forming an adhesive contact portion over the platinum contact portion, forming a barrier contact portion over the adhesive contact portion, and forming a gold contact portion over the barrier contact portion. The method further comprises annealing the semiconductor structure to alloy the platinum contact portion with the N-type doped semiconductor contact layer to form a platinum/semiconductor alloyed diffusion contact barrier substantially disposed within the N-type doped semiconductor contact layer.

Abstract: A semiconductor device (100) is formed on a semi-insulating semiconductor substrate (101) including a channel layer (104), a spacer layer (105), an electron supply layer (106), and a barrier layer (108). A composite layer (110) is formed over the barrier layer (108). A metal (116) is deposited over the composite layer (110). The metal (116) is annealed to promote a chemical reaction between the metal (116) and the composite layer (110) in which a portion of the metal sinks into the composite layer (110) and forms an ohmic contact with the composite layer.

Abstract: In a method of forming a semiconductor device on a semiconductor substrate (100), a photoresist layer (102) is deposited on the semiconductor substrate; a window (106) is formed in the photoresist layer (102) by electron beam lithography; a conformal layer (108) is deposited on the photoresist layer (102) and in the window (106); and substantially all of the conformal layer (108) is selectively removed from the photoresist layer (102) and a bottom portion of the window to form dielectric sidewalls (110) in the window (106).