Abstract: The present disclosure provides for improving data retention reliability. During a programming operation associated with a memory cell, after the memory cell passes verification of a first verification voltage level, a second verification voltage level can be applied to the memory cell. Based on a comparison of the voltage in the memory cell with the second verification voltage level, a bit line voltage may be applied. Based on the applied bit line voltage, fast bits associated with the memory cell can be upshifted to an upper portion of a final voltage distribution associated with the programming operation. Upshifting the fast bits counteracts the downshifting effect in a final voltage distribution that may be caused by charge leakage or electron loss.

Abstract: A method for performing an erase operation of a partially programmed memory block of a non-volatile memory structure. The method comprises: (1) applying an erase voltage bias level to a channel region of the memory block, (2) applying a word line voltage level to all programmed word line(s) of the memory block, (3) applying a “float” condition to all unprogrammed word line(s) of the memory block, and (4) applying an erase verify operation to all word line(s) of the memory block, wherein the “float” condition comprises omitting application of the word line voltage to the unprogrammed word line(s).

Abstract: A method for performing an erase operation of a partially programmed memory block of a non-volatile memory structure. The method comprises: (1) applying an erase voltage bias level to a channel region of the memory block, (2) applying a word line voltage level to all programmed word line(s) of the memory block, (3) applying a “float” condition to all unprogrammed word line(s) of the memory block, and (4) applying an erase verify operation to all word line(s) of the memory block, wherein the “float” condition comprises omitting application of the word line voltage to the unprogrammed word line(s).

Abstract: The present disclosure provides for improving data retention reliability. During a programming operation associated with a memory cell, after the memory cell passes verification of a first verification voltage level, a second verification voltage level can be applied to the memory cell. Based on a comparison of the voltage in the memory cell with the second verification voltage level, a bit line voltage may be applied. Based on the applied bit line voltage, fast bits associated with the memory cell can be upshifted to an upper portion of a final voltage distribution associated with the programming operation. Upshifting the fast bits counteracts the downshifting effect in a final voltage distribution that may be caused by charge leakage or electron loss.

Abstract: Provided is a semiconductor device having a dual gate field-effect transistor and a sensor in electrical communication with the transistor. The field-effect transistor can have a first gate electrode, a second gate electrode, a source electrode, a drain electrode, a semiconductor layer with parts in contact with the source and drain electrodes, a bi-layer gate insulator, and a second gate insulator. The bi-layer gate insulator can include a first layer and a second layer, the first layer located between the second layer and a first side of the semiconductor layer, the second layer located between the first layer and the first gate electrode. The second gate insulator can be located between the second gate electrode and a second side of the semiconductor layer, and the sensor can be in electrical communication with the second gate electrode.