Abstract: Methods, systems, and devices for object detection are described. A device may receive an image, and detect, via a first stage of a cascade neural network, object recognition information over one or more angular orientations during a first pass. The device may determine, via a second stage of the cascade neural network, a confidence score associated with one or more of the candidate object in the image, the candidate bounding box associated with the candidate object in the image, or one or more object features of the candidate object in the image, or an orientation of the candidate object in the image, or a combination thereof. The device may identify, via a third stage of the cascade neural network, whether to detect the object recognition information during a second pass based on the confidence score satisfying a threshold.

Abstract: Methods, systems, and devices for object detection are described. A device may receive an image, and detect, via a first stage of a cascade neural network, object recognition information over one or more angular orientations during a first pass. The device may determine, via a second stage of the cascade neural network, a confidence score associated with one or more of the candidate object in the image, the candidate bounding box associated with the candidate object in the image, or one or more object features of the candidate object in the image, or an orientation of the candidate object in the image, or a combination thereof. The device may identify, via a third stage of the cascade neural network, whether to detect the object recognition information during a second pass based on the confidence score satisfying a threshold.

Abstract: A data latch includes a first stage configured to receive an input in a first voltage domain, and a second stage. The second stage includes a level shifter configured to shift the input from the first voltage domain to a second voltage domain, and an output circuit having a pull down circuit and pull up circuit arranged to generate an output in the second voltage domain, wherein the pull down circuit is responsive to the input in the first voltage domain and the pull up circuit is responsive to the input in the second voltage domain.

Abstract: An output driver for electrostatic discharge (ESD) protection includes a first pair of stacked metal oxide semiconductor field-effect transistor (MOS) devices coupled between a power terminal and a first differential output terminal. The output driver also includes a second pair of stacked MOS devices coupled between a second differential output terminal and a ground terminal.

Abstract: An output driver for electrostatic discharge (ESD) protection includes a first pair of stacked metal oxide semiconductor field-effect transistor (MOS) devices coupled between a power terminal and a first differential output terminal. The output driver also includes a second pair of stacked MOS devices coupled between a second differential output terminal and a ground terminal.

Abstract: A method and circuit for characterizing a process variation of a semiconductor die is disclosed. In a particular embodiment, the method includes operating a circuit at multiple supply voltage levels to generate race condition testing data. The circuit is disposed on at least one die of a wafer and includes at least one racing path circuit having at least two paths. The method further includes collecting the race condition testing data and evaluating the collected race condition testing data. The race condition testing data is correlated to a process variation of the at least one die.

Abstract: Systems and method for defining a timing parameter for a circuit element based on process variation, including, determining a point of failure parameter associated with the timing parameter, the point of failure parameter correlated with a specific value of the process variation. A standard deviation associated with the point of failure parameter is determined. The process variation per the standard deviation is calculated and the timing parameter for the circuit element is defined as a function of the failure parameter, the standard deviation, and the process variation per the standard deviation. A margin factor, which varies with the standard deviation, is optionally applied to the timing parameter. The timing parameter may be one of a setup time or hold time.

Abstract: Systems and method for defining a timing parameter for a circuit element based on process variation, including, determining a point of failure parameter associated with the timing parameter, the point of failure parameter correlated with a specific value of the process variation. A standard deviation associated with the point of failure parameter is determined. The process variation per the standard deviation is calculated and the timing parameter for the circuit element is defined as a function of the failure parameter, the standard deviation, and the process variation per the standard deviation. A margin factor, which varies with the standard deviation, is optionally applied to the timing parameter. The timing parameter may be one of a setup time or hold time.

Abstract: A method and circuit for characterizing a process variation of a semiconductor die is disclosed. In a particular embodiment, the method includes operating a circuit at multiple supply voltage levels to generate race condition testing data. The circuit is disposed on at least one die of a wafer and includes at least one racing path circuit having at least two paths. The method further includes collecting the race condition testing data and evaluating the collected race condition testing data. The race condition testing data is correlated to a process variation of the at least one die.

Abstract: A method, system and computer program product for determining aggressor-induced crosstalk in a victim net of a stage of an integrated circuit design is provided. The methodology can include combining a plurality of aggressor nets to construct a virtual aggressor net, determining a current waveform induced on the victim net by the plurality of small aggressor nets, and modeling a current waveform induced by the virtual aggressor on the victim net based on the contribution of the current waveforms determined for the plurality of small aggressor nets. In a further embodiment, the methodology can also comprise evaluating an effect of an aggressor net on a victim net; and including that aggressor net in the virtual aggressor net if its effect is below a predetermined threshold. The effect evaluated by the methodology can, for example, be the height of a glitch induced on the victim net by a transition in the aggressor net.

Abstract: A memory logic built-in self-test (“BIST”) includes slow speed controller-to-collar signals, while allowing collars to test memories at full speed. A controller is configured to include control features and address, data, read/write, output evaluation, and redundancy calculation values are configured within the collars. The controller is further configured to handle scheduling of the collars and diagnostics interfacing. In addition, the collars are configured to allow BIST testing to be run serially, in parallel, or in groups. Collars are also configured to send diagnostic results back to the controller based on the initialization of the respective collars, thus providing a central interface for the diagnostics results.

Abstract: A method for generating a software-based self-test in an integrated circuit includes extracting constraints for corresponding instructions for the integrated circuit, modeling the constraints for a plurality of timeframes and performing constrained test pattern generation on the integrated circuit using the models. An automatic test pattern generation method for an AC fault in an integrated circuit includes identifying a current desired condition for triggering the AC fault, determining whether the current desired condition is feasible, and identifying a subsequent desired condition for triggering the AC fault if the current desired condition is not feasible. The method further includes determining whether the subsequent desired condition for triggering the AC fault is feasible, and searches for test vectors for realizing the current desired condition or subsequent desired condition which is determined to be feasible.

Abstract: A method for optimizing the design of a chip or system by decreasing the cost function that encompasses a plurality of constraints in the presence of variations in the design parameters is described. The method makes use of numerical optimization, simulated annealing, or any other objective-driven optimization means, and accounts for uncertainties in the modeling of the design variables and functions. A significant reduction in the number of design constraints which are violated at the end of an optimization process is achieved, even when all the design constraints cannot be satisfied. The optimization also reduces the cycle time at which the design operates and limits the increase in the minimum operational cycle time of a particular implementation in the presence of variations that cannot be modeled or unpredictable variations in delay introduced by elements of the design.

Abstract: A method for optimizing the design of a chip or system by decreasing the cost function that encompasses a plurality of constraints in the presence of variations in the design parameters is described. The method makes use of numerical optimization, simulated annealing, or any other objective-driven optimization means, and accounts for uncertainties in the modeling of the design variables and functions. A significant reduction in the number of design constraints which are violated at the end of an optimization process is achieved, even when all the design constraints cannot be satisfied. The optimization also reduces the cycle time at which the design operates and limits the increase in the minimum operational cycle time of a particular implementation in the presence of variations that cannot be modeled or unpredictable variations in delay introduced by elements of the design.