Patents by Inventor Xiaoling Xu
Xiaoling Xu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8671304Abstract: A method, system, and computer program product are provided for adjusting write timing in a memory device based on a training signal. For instance, the method can include configuring the memory device in a training mode of operation. The method can also include determining a write timing window between a signal on a data bus and a write clock signal based on the training signal. Further, the method includes adjusting a phase difference between the signal on the data bus and the write clock signal based on the write timing window. The memory device can recover data on the data bus based on the adjusted phase difference.Type: GrantFiled: July 30, 2010Date of Patent: March 11, 2014Assignee: Advanced Micro Devices, Inc.Inventors: Aaron John Nygren, Ming-Ju Edward Lee, Shadi M. Barakat, Xiaoling Xu, Toan Duc Pham, Warren Fritz Kruger
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Publication number: 20130290767Abstract: Apparatuses are provided for adjusting the write timing. For instance, the apparatus can include an address/control bus, a write clock data recovery (WCDR) signal bus, and a timing adjustment module. The address/control bus can be configured to concurrently enable a WCDR mode of operation and an active mode of operation. The WCDR signal bus can be configured to transmit WCDR data to a memory device during the WCDR mode of operation. And the timing adjustment module can be configured to adjust a timing based on a phase shift in the WCDR data.Type: ApplicationFiled: June 18, 2013Publication date: October 31, 2013Inventors: Aaron J. NYGREN, Ming-Ju E. Lee, Shadi M. Barakat, Xiaoling Xu, Toan D. Pham, W. Fritz Kruger, Michael J. Litt
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Patent number: 8489912Abstract: A method, system, and computer program product are provided for adjusting write timing in a memory device based on a command protocol. For instance, the method can include enabling a write clock data recovery (WCDR) mode of operation. The method can also include transmitting WCDR data from a processing unit to the memory device during the WCDR mode of operation and another mode of operation of the memory device. Based on a phase shift in the WCDR data, a phase difference between a signal on a data bus and a write clock signal can be adjusted. Further, the method can include transmitting the signal on the data bus based on the adjusted phase difference between the signal on the data bus and the write clock signal.Type: GrantFiled: July 30, 2010Date of Patent: July 16, 2013Assignee: ATI Technologies ULCInventors: Aaron John Nygren, Ming-Ju Edward Lee, Shadi M. Barakat, Xiaoling Xu, Toan Duc Pham, Warren Fritz Kruger, Michael John Litt
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Publication number: 20130141685Abstract: Another embodiment of the present invention provides an array substrate and a liquid crystal display. The array substrate comprises a plurality of gate lines and a plurality of data lines, and the gate lines and the data lines intersect each other to define a plurality of sub-pixel regions; each sub-pixel region comprises a first transparent electrode, a second transparent electrode and a thin film transistor (TFT), and in the sub-pixel region, a first edge of the second transparent electrode away from the TFT and along the direction of the gate lines is parallel to a second edge of a gate line for an adjacent sub-pixel region, and the second edges is the edge, closest to the first edge, of the gate line for the adjacent sub-pixel region.Type: ApplicationFiled: December 4, 2012Publication date: June 6, 2013Applicant: BOE TECHNOLOGY GROUP CO., LTD.Inventors: Xiaoling Xu, Jaegeon You
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Patent number: 8443225Abstract: Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device.Type: GrantFiled: August 13, 2012Date of Patent: May 14, 2013Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Aaron Nygren, Ming-Ju Edward Lee, Shadi Barakat, Xiaoling Xu, Toan Duc Pham, Warren Fritz Kruger, Michael Litt
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Patent number: 8412912Abstract: In various embodiments, dedicated mask pins are eliminated by sending a data mask on address lines of the interface. A memory controller receives a request for a memory write operation from a memory client and determines the granularity of the write data from a write data mask sent by the client. Granularity, as used herein, indicates a quantity of write data to which each bit of the received write data mask applies. In an embodiment, the memory controller generates a particular write command and a particular write data mask based on the granularity of the write data. The write command generated is typically the most efficient of several write commands available, but embodiments are not so limited. The write command is transmitted on command lines of the interface, and the write data mask is transmitted on address lines of the interface.Type: GrantFiled: May 2, 2012Date of Patent: April 2, 2013Assignee: ATI Technologies ULCInventors: Xiaoling Xu, Warren F. Kruger
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Publication number: 20130052177Abstract: Isolated monomelic aminoacyl-tRNA synthetase polypeptides and polynucleotides having non-canonical biological activities are provided, as well as compositions and methods related thereto.Type: ApplicationFiled: February 4, 2011Publication date: February 28, 2013Applicant: The Scripps Research InstituteInventors: Paul Schimmel, Xiang-Lei Yang, Bonnie Slike, Xiaoling Xu, Min Guo
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Publication number: 20120303995Abstract: Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device.Type: ApplicationFiled: August 13, 2012Publication date: November 29, 2012Applicants: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULCInventors: Aaron Nygren, Ming-Ju Edward Lee, Shadi Barakat, Xiaoling Xu, Toan Duc Pham, Warren Fritz Kruger, Michael Litt
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Patent number: 8275972Abstract: In various embodiments, dedicated mask pins are eliminated by sending a data mask on address lines of the interface. A memory controller receives a request for a memory write operation from a memory client and determines the granularity of the write data from a write data mask sent by the client. Granularity, as used herein, indicates a quantity of write data to which each bit of the received write data mask applies. In an embodiment, the memory controller generates a particular write command and a particular write data mask based on the granularity of the write data. The write command generated is typically the most efficient of several write commands available, but embodiments are not so limited. The write command is transmitted on command lines of the interface, and the write data mask is transmitted on address lines of the interface.Type: GrantFiled: August 23, 2006Date of Patent: September 25, 2012Assignee: ATI Technologies, Inc.Inventors: Xiaoling Xu, Warren F. Kruger
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Publication number: 20120215996Abstract: In various embodiments, dedicated mask pins are eliminated by sending a data mask on address lines of the interface. A memory controller receives a request for a memory write operation from a memory client and determines the granularity of the write data from a write data mask sent by the client. Granularity, as used herein, indicates a quantity of write data to which each bit of the received write data mask applies. In an embodiment, the memory controller generates a particular write command and a particular write data mask based on the granularity of the write data. The write command generated is typically the most efficient of several write commands available, but embodiments are not so limited. The write command is transmitted on command lines of the interface, and the write data mask is transmitted on address lines of the interface.Type: ApplicationFiled: May 2, 2012Publication date: August 23, 2012Applicant: ATI TECHNOLOGIES INC.Inventors: Xiaoling XU, Warren F. KRUGER
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Patent number: 8245073Abstract: Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device.Type: GrantFiled: July 24, 2009Date of Patent: August 14, 2012Assignee: Advanced Micro Devices, Inc.Inventors: Aaron Nygren, Ming-Ju Edward Lee, Shadi Barakat, Xiaoling Xu, Toan Duc Pham, Warren Fritz Kruger, Michael Litt
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Publication number: 20120105754Abstract: Embodiments of the disclosed technology provide a TFT-LCD and manufacturing method and driving method thereof. The TFT-LCD comprises a color filter substrate, an array substrate, and a liquid crystal layer sandwiched between the color filter substrate and the array substrate. A first strip-like electrode and a second strip-like electrode are formed in the area of a black matrix on the color filter substrate, an area surrounded by the first strip-like electrode and the second strip-like electrode comprises at least one sub-pixel area, and the first strip-like electrode and second strip-like electrode are electrically insulated from each other.Type: ApplicationFiled: October 28, 2011Publication date: May 3, 2012Applicant: BOE TECHNOLOGY GROUP CO., LTD.Inventors: Jianlei ZHU, Xiaoling XU, Jaegeon YOU
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Patent number: 8032209Abstract: Described herein is a non-invasive determination of locations of neural activity in a brain. In particular, methods and systems have been developed that utilize a FINES algorithm for use in three-dimensional (3-D) dipole source localization to locate neural activity in a brain.Type: GrantFiled: March 9, 2006Date of Patent: October 4, 2011Assignees: Regents of the University of Minnesota, Board of Trustees of the University of IllinoisInventors: Bin He, Xiaoling Xu, Bobby Xu
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Publication number: 20110208989Abstract: A method, system, and computer program product are provided for adjusting write timing in a memory device based on a command protocol. For instance, the method can include enabling a write clock data recovery (WCDR) mode of operation. The method can also include transmitting WCDR data from a processing unit to the memory device during the WCDR mode of operation and another mode of operation of the memory device. Based on a phase shift in the WCDR data, a phase difference between a signal on a data bus and a write clock signal can be adjusted. Further, the method can include transmitting the signal on the data bus based on the adjusted phase difference between the signal on the data bus and the write clock signal.Type: ApplicationFiled: July 30, 2010Publication date: August 25, 2011Applicant: Advanced Micro Devices, Inc.Inventors: Aaron John Nygren, Ming-Ju Edward Lee, Shadi M. Barakat, Xiaoling Xu, Toan Duc Pham, Warren Fritz Kruger, Michael John Litt
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Publication number: 20110185218Abstract: A method, system, and computer program product are provided for adjusting write timing in a memory device based on a training signal. For instance, the method can include configuring the memory device in a training mode of operation. The method can also include determining a write timing window between a signal on a data bus and a write clock signal based on the training signal. Further, the method includes adjusting a phase difference between the signal on the data bus and the write clock signal based on the write timing window. The memory device can recover data on the data bus based on the adjusted phase difference.Type: ApplicationFiled: July 30, 2010Publication date: July 28, 2011Applicant: Advanced Micro Devices, Inc.Inventors: Aaron John Nygren, Ming-Ju Edward Lee, Shadi M. Barakat, Xiaoling Xu, Toan Duc Pham, Warren Fritz Kruger
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Publication number: 20110185256Abstract: A method, system, and computer program product are provided for adjusting write timing in a memory device based on results of an error detection function. For instance, the method can include determining a write timing window between a signal on a data bus and a write clock signal based on the results of the error detection function. The method can also include adjusting a phase difference between the signal on the data bus and the write clock signal based on the write timing window. The memory device can recover data on the data bus based on the adjusted phase difference.Type: ApplicationFiled: July 30, 2010Publication date: July 28, 2011Applicant: Advanced Micro Devices, Inc.Inventors: Aaron John Nygren, Ming-Ju Edward Lee, Shadi M. Barakat, Xiaoling Xu, Toan Duc Pham, Warren Fritz Kruger
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Publication number: 20110019787Abstract: Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device.Type: ApplicationFiled: July 24, 2009Publication date: January 27, 2011Inventors: Aaron Nygren, Ming-Ju Edward Lee, Shadi Barakat, Xiaoling Xu, Toan Duc Pham, Warren Fritz Kruger, Michael Litt
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Publication number: 20100329045Abstract: A method and system are provided for adjusting a write timing in a memory device. For instance, the method can include receiving a data signal, a write clock signal, and a reference signal. The method can also include detecting a phase shift in the reference signal over time. The phase shift of the reference signal can be used to adjust a phase difference between the data signal and the write clock signal, where the memory device recovers data from the data signal based on an adjusted write timing of the data signal and the write clock signal.Type: ApplicationFiled: June 24, 2009Publication date: December 30, 2010Applicant: Advanced Micro Devices, Inc.Inventors: Ming-Ju Edward LEE, Shadi M. Barakat, Warren Fritz Kruger, Xiaoling Xu, Toan Duc Pham, Aaron John Nygren
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Publication number: 20080052474Abstract: In various embodiments, dedicated mask pins are eliminated by sending a data mask on address lines of the interface. A memory controller receives a request for a memory write operation from a memory client and determines the granularity of the write data from a write data mask sent by the client. Granularity, as used herein, indicates a quantity of write data to which each bit of the received write data mask applies. In an embodiment, the memory controller generates a particular write command and a particular write data mask based on the granularity of the write data. The write command generated is typically the most efficient of several write commands available, but embodiments are not so limited. The write command is transmitted on command lines of the interface, and the write data mask is transmitted on address lines of the interface.Type: ApplicationFiled: August 23, 2006Publication date: February 28, 2008Inventors: Xiaoling Xu, Warren F. Kruger
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Publication number: 20060251303Abstract: Described herein is a non-invasive determination of locations of neural activity in a brain. In particular, methods and systems have been developed that utilize a FINES algorithm for use in three-dimensional (3-D) dipole source localization to locate neural activity in a brain.Type: ApplicationFiled: March 9, 2006Publication date: November 9, 2006Inventors: Bin He, Xiaoling Xu, Bobby Xu