Abstract: The present disclosure provides a three-dimensional memory device and a manufacturing method thereof, the three-dimensional memory device including: a plurality of stacked layers; a storage channel structure vertically penetrating the stacked layers and comprising a first channel layer; a select gate structure on the plurality of stacked layers; and a select channel structure vertically penetrating the select gate structure and comprising a second channel layer; wherein an outer sidewall of the second channel layer is in contact with an inner sidewall of the first channel layer.

Abstract: The present disclosure provides a three-dimensional memory comprising: a storage channel structure vertically penetrating a plurality of stacked layers and comprising a first channel layer; a select gate structure on the plurality of stacked layers; and a select channel structure vertically penetrating the select gate structure and comprising: a block layer in contact with the select gate structure, an insulating layer covering the block layer, and a second channel layer in contact with the insulating layer and the first channel layer.

Abstract: The present disclosure provides a three-dimensional memory device and a manufacturing method thereof. The three-dimensional memory device comprises: a plurality of stacked layers; a storage channel structure vertically penetrating the stacked layers and comprising a first channel layer; a select gate structure on the plurality of stacked layers and comprising a conductive layer sandwiched between two dielectric layers; and a select channel structure vertically penetrating the select gate structure and comprising a second channel layer.

Abstract: According to an aspect of the disclosure, a semiconductor device is provided. The semiconductor device includes a stack structure that includes alternating insulating layers and word line layers. The semiconductor device also includes a first channel structure extending through the stack structure, a first top select gate (TSG) layer over the stack structure, and a second TSG layer over the first TSG layer. The semiconductor device further includes a second channel structure extending through the first and second TSG layers, where the second channel structure is positioned over and coupled to the first channel structure.

Abstract: The present invention provides a display panel and manufacturing method thereof, the method including following steps: providing a driving backplane and a light-emitting substrate, and bonding the driving backplane and the light-emitting substrate; patterning the light-emitting substrate to form a pixel array; forming a thin film packaging layer on an outside of the pixel array, the thin film packaging layer completely covering the pixel array; forming quantum dots on top of the thin film packaging layer to form a multi-color display; forming a reflective array between two adjacent quantum dots to avoid optical crosstalk between the pixel arrays. The display panel and the method of the present invention break through the physical limit of the high PPI, high-precision metal mask, which can realize the display of 2000 and higher PPI, and can prevent the optical crosstalk between the pixel arrays.

Abstract: Provided is a T lymphocyte. The T lymphocyte expresses a chimeric antigen receptor, and includes an extracellular region. The extracellular region includes a first single-chain antibody, a second single-chain antibody, a first linker peptide, and a CD8 hinge region. The first linker peptide is arranged between the first single-chain antibody and the second single-chain antibody. The first single-chain antibody includes a first heavy chain variable region, a first light chain variable region, and a second linker peptide. The second linker peptide is arranged between the first heavy chain variable region and the first light chain variable region. The second single-chain antibody includes a second heavy chain variable region, a second light chain variable region, and a third linker peptide. The third linker peptide is arranged between the second heavy chain variable region and the second light chain variable region.

Abstract: Provided is an antibody or antigen-binding fragment thereof that can specifically recognize CD22. The antibody contains a CDR sequence selected from at least one of the following or an amino acid sequence at least 95% identical thereto: a heavy-chain variable region CDR sequence: SEQ ID NOs: 1-15, and a light-chain variable region CDR sequence as shown in SEQ IN NOs: 16-30. The antibody can specifically recognize CD22 and has high affinity to CD22.

Abstract: A method for forming a three-dimensional memory device includes forming an alternating dielectric stack on a substrate and forming an opening extending partially through the alternating dielectric stack. The opening exposes sidewalls of the alternating dielectric stack. The method also includes disposing a protection layer in the opening and on the exposed sidewalls of the alternating dielectric stack. The method further includes extending the opening through the alternating dielectric stack and forming channel layers in the extended opening.

Abstract: Provided is a T lymphocyte. The T lymphocyte co-expresses a fusion protein and a chimeric antigen receptor, and the chimeric antigen receptor identifies a tumor antigen, herein the chimeric antigen receptor includes: an extracellular region; a transmembrane region, herein the transmembrane region is connected to the extracellular region, and embedded into a cell membrane of a transgenic lymphocyte; and an intracellular region, herein the intracellular region is connected to the transmembrane region, and the intracellular region includes an immune co-stimulatory molecule intracellular segment. The fusion protein includes: an immune checkpoint single-chain antibody and a T cell activation molecule.

Abstract: The three-dimensional memory includes a stack structure which includes: a first stack and a second stack, the first stack including control gate layers and first dielectric layers which are stacked alternately, the second stack including top select gate layers and second dielectric layers which are stacked alternately in the same stacking direction; a plurality of channel structures which run though the stack structure and include charge storage layers, the charge storage layers including a plurality of charge storage portions disposed discontinuously in the stacking direction, the charge storage portions being disposed between the adjacent first dielectric layers; and at least one isolation structure which runs through the top select gate layers and is located between the adjacent channel structures.

Abstract: A three-dimensional (3D) memory device includes a doped semiconductor layer, a stack structure, a channel structure, and a semiconductor structure. The stack structure includes a plurality of word lines and a select gate line formed on the doped semiconductor layer. The channel structure extends through the plurality of word lines along a first direction and in contact with the doped semiconductor layer. The semiconductor structure extends through the select gate line along the first direction and in contact with the channel structure. The select gate line extends along a second direction perpendicular to the first direction, and the drain select gate line around the semiconductor structure is insulated from the drain select gate line around an adjacent semiconductor structure. A width of the semiconductor structure is less than a width of the channel structure.

Abstract: The present application provides a three-dimensional memory and a fabrication method for the same. The method includes forming a storage stack structure on a substrate and forming a storage channel structure that penetrates the storage stack structure, forming a selection stack structure stacked on the storage stack structure and forming a selection channel structure that penetrates the selection stack structure and is connected to the storage channel structure. The width of the selection channel structure is smaller than the width of the storage channel structure on a plane parallel to the substrate and forming a TSG cut structure that penetrates the selection stack structure. The three-dimensional memory and the fabrication method for the same increases the process window for the TSG cut structure formed between the selection channel structures and improves the storage density.

Abstract: A method for forming a three-dimensional memory device includes forming an alternating dielectric stack on a substrate and forming an opening extending partially through the alternating dielectric stack. The opening exposes sidewalls of the alternating dielectric stack. The method also includes disposing a protection layer in the opening and on the exposed sidewalls of the alternating dielectric stack. The method further includes extending the opening through the alternating dielectric stack and forming channel layers in the extended opening.

Abstract: Embodiments are directed to a flexible high voltage thin film transistor (f-HVTFT) with a center-symmetric circular configuration. The f-HVTFT includes a ring-shaped oxide semiconductor channel, a ring-shaped gate, a ring-shaped source, and a circular drain. The source and gate each have multiple connections to respective electrode pads, enabling stable and identical electrical characteristics and blocking voltage while the f-HVTFT is subject to bending from random directions. The f-HVTFT enables a high blocking voltage over 100 V, on-current over 100 ?A, and low off-current of 0.1 pA, which makes it suitable for power management of self-powered wearable electronic systems.

Abstract: Embodiments are directed to a flexible high voltage thin film transistor (f-HVTFT) with a center-symmetric circular configuration. The f-HVTFT includes a ring-shaped oxide semiconductor channel, a ring-shaped gate, a ring-shaped source, and a circular drain. The source and gate each have multiple connections to respective electrode pads, enabling stable and identical electrical characteristics and blocking voltage while the f-HVTFT is subject to bending from random directions. The f-HVTFT enables a high blocking voltage over 100 V, on-current over 100 ?A, and low off-current of 0.1 pA, which makes it suitable for power management of self-powered wearable electronic systems.

Abstract: The present invention provides a preparation method for a fully-transparent thin film transistor, wherein a transparent conductive gate electrode layer of the fully-transparent thin film transistor is used as a photolithographic mask, a photoresist is exposed through a rear surface of a transparent substrate, the transparent substrate has a transmittance higher than 60% to an exposure light beam, and the transparent conductive gate electrode layer has a transmittance lower than 5% to the exposure light beam. In the preparation method for a fully-transparent thin film transistor provided by the present invention, by using a self-aligned technology, the process complexity and the feature size of the device can both be reduced.

Abstract: The present invention provides a preparation method for a fully-transparent thin film transistor, wherein a transparent conductive gate electrode layer of the fully-transparent thin film transistor is used as a photolithographic mask, a photoresist is exposed through a rear surface of a transparent substrate, the transparent substrate has a transmittance higher than 60% to an exposure light beam, and the transparent conductive gate electrode layer has a transmittance lower than 5% to the exposure light beam. In the preparation method for a fully-transparent thin film transistor provided by the present invention, by using a self-aligned technology, the process complexity and the feature size of the device can both be reduced.

Abstract: The present invention concerns a high vacuum in-situ refining method for high-purity and superhigh-purity materials and the apparatus thereof, characterized in heating the upper part and lower part of crucible separately using double-heating-wires diffusion furnace under vacuum, thereby forming the temperature profile which is high at upper part and low at lower part of crucible, or in reverse during different stages; then heating the crucible in two steps to remove impurities with high saturation vapor pressure and low saturation vapor pressure respectively in efficiency; and obtaining high-purity materials eventually. The whole procedure is isolated from atmosphere, reducing contamination upon stuff remarkably. The present invention could provide products with high-quality and high production capacity, which are stable in performance, therefore is reliable and free from contamination.

Abstract: There is provided a method of manufacturing high quality ZnO manufacturing film on silicon (111) substrate, including the following steps: removing silicon oxide on the surface of silicon (111) substrate; depositing metal monocrystal film having 1-10 nm thickness, such as Mg, Ca, Sr, Cd etc, at low temperature; oxiding the metal film at low temperature to obstain metal oxide monocrystal layer; depositing ZnO buffer layer at low temperature; depositing ZnO epitaxial layer at high temperature. The ZnO film is suitable for fabrication of high performance of photoelectron device.