Abstract: An apparatus includes a metal gate, a substrate material, and an oxide layer between the metal gate and the substrate material. The oxide layer includes a hafnium oxide layer contacting the metal gate and a silicon dioxide layer contacting the substrate material and contacting the hafnium oxide layer. The metal gate, the substrate material, and the oxide layer are included in a one-time programmable (OTP) memory device. The OTP memory device includes a transistor. A non-volatile state of the OTP memory device is based on a threshold voltage shift of the OTP memory device.

Abstract: Memory programming methods and memory systems are described. One example memory programming method includes first applying a first signal to a memory cell to attempt to program the memory cell to a desired state, wherein the first signal corresponds to the desired state, after the first applying, determining that the memory cell failed to place in the desired state, after the determining, second applying a second signal to the memory cell, wherein the second signal corresponds to another state which is different than the desired state, and after the second applying, third applying a third signal to the memory cell to program the memory cell to the desired state, wherein the third signal corresponds to the desired state. Additional method and apparatus are described.

Abstract: An apparatus includes a static random-access memory and circuitry configured to initiate a corrective action associated with the static random-access memory. The corrective action may be initiated based on a number of static random-access memory cells that have a particular state responsive to a power-up of the static random-access memory.

Abstract: Memory programming methods and memory systems are described. One example memory programming method includes first applying a first signal to a memory cell to attempt to program the memory cell to a desired state, wherein the first signal corresponds to the desired state, after the first applying, determining that the memory cell failed to place in the desired state, after the determining, second applying a second signal to the memory cell, wherein the second signal corresponds to another state which is different than the desired state, and after the second applying, third applying a third signal to the memory cell to program the memory cell to the desired state, wherein the third signal corresponds to the desired state. Additional method and apparatus are described.

Abstract: Embodiments disclosed herein may relate to programming a memory cell with a programming pulse that comprises a quenching period having different portions. The memory cell may have more than two possible programmed states, where each programmed state of the memory cell includes a different fraction of amorphous material. A memory element may be melted and then quenched. The fraction of amorphous material, and thus the programmed state, may be controlled by selecting one of multiple quenching periods for the programming pulse.

Abstract: Non-volatile memory devices and logic devices are fabricated using processes compatible with high dielectric constant/metal gate (HK/MG) processes for increased cell density and larger scale integration. A doped oxide layer, such as a silicon-doped hafnium oxide (HfO2) layer, is implemented as a ferroelectric dipole layer in a nonvolatile memory device.

Abstract: An apparatus includes a multiple time programmable (MTP) memory device. The MTP memory device includes a metal gate, a substrate material, and an oxide structure between the metal gate and the substrate material. The oxide structure includes a hafnium oxide layer and a silicon dioxide layer. The hafnium oxide layer is in contact with the metal gate and in contact with the silicon dioxide layer. The silicon dioxide layer is in contact with the substrate material. The MTP device includes a transistor, and a non-volatile state of the MTP memory device is based on a threshold voltage of the transistor.

Abstract: An OTP memory array includes a plurality of differential P-channel metal oxide semiconductor (PMOS) OTP memory cells programmable and readable in predetermined states of program and read operations, and is capable of providing sufficient margins against global process variations and temperature variations while being compatible with standard logic fin-shaped field effect transistor (FinFET) processes to obviate the need for additional masks and costs associated with additional masks.

Abstract: A volatile and one-time program (OTP) compatible asymmetric memory cell may include a first pull-up transistor having a first threshold voltage. The asymmetric memory cell may also include a second pull-up transistor having a second threshold voltage that differs from the first threshold voltage. The asymmetric memory cell may further include a switch coupled to a well of the first pull-up transistor and the second pull-up transistor to alternate between a program voltage (Vpg) and a power supply voltage. The asymmetric memory cell may also include a peripheral switching circuit to control programming of the asymmetric memory cell.

Abstract: An OTP memory array includes a plurality of differential P-channel metal oxide semiconductor (PMOS) OTP memory cells programmable and readable in predetermined states of program and read operations, and is capable of providing sufficient margins against global process variations and temperature variations while being compatible with standard logic fin-shaped field effect transistor (FinFET) processes to obviate the need for additional masks and costs associated with additional masks.

Abstract: A semiconductor device for a one-time programmable (OTP) memory according to some examples of the disclosure includes a gate, a dielectric region below the gate, a source terminal below the dielectric region and offset to one side, a drain terminal below the dielectric region and offset to an opposite side from the source terminal, a drain side charge trap in the dielectric region capable of programming the semiconductor device, and a source side charge trap in the dielectric region opposite the drain side charge trap and capable of programming the semiconductor device.

Abstract: A method of operation of a static random access memory (SRAM) storage element includes programming a value to the SRAM storage element prior to a power-down event. The method further includes, in response to a power-on event at the SRAM storage element after the power-down event, increasing a supply voltage of the SRAM storage element and sensing a state of the SRAM storage element to determine the value programmed to the SRAM storage element prior to the power-down event. In a particular example, an apparatus includes the SRAM storage element and control circuitry coupled to the SRAM storage element. The control circuitry may be configured to program the value to the SRAM storage element, to increase the supply voltage, and to sense the state of the SRAM storage element to determine the value programmed to the SRAM storage element prior to the power-down event.

Abstract: An apparatus includes a static random-access memory and circuitry configured to initiate a corrective action associated with the static random-access memory. The corrective action may be initiated based on a number of static random-access memory cells that have a particular state responsive to a power-up of the static random-access memory.

Abstract: A method of forming a resistive memory element comprises forming an oxide material over a first electrode. The oxide material is exposed to a plasma process to form a treated oxide material. A second electrode is formed on the treated oxide material. Additional methods of forming a resistive memory element, as well as related resistive memory elements, resistive memory cells, and resistive memory devices are also described.

Abstract: Aspects disclosed in the detailed description include high-k (HK)/metal gate (MG) (HK/MG) multi-time programmable (MTP) switching devices, and related systems and methods. One type of HK/MG MTP switching device is an MTP metal-oxide semiconductor (MOS) field-effect transistor (MOSFET). When the MTP MOSFET is programmed, a charge trap may build up in the MTP MOSFET due to a switching electrical current induced by a switching voltage. The charge trap reduces the switching window and endurance of the MTP MOSFET, thus reducing reliability in accessing the information stored in the MTP MOSFET. In this regard, an HK/MG MTP switching device comprising the MTP MOSFET is configured to eliminate the switching electrical current when the MTP MOSFET is programmed. By eliminating the switching electrical current, it is possible to avoid a charge trap in the MTP MOSFET, thus restoring the switching window and endurance of the MTP MOSFET for reliable information access.

Abstract: A method of operation of a static random access memory (SRAM) storage element includes programming a value to the SRAM storage element prior to a power-down event. The method further includes, in response to a power-on event at the SRAM storage element after the power-down event, increasing a supply voltage of the SRAM storage element and sensing a state of the SRAM storage element to determine the value programmed to the SRAM storage element prior to the power-down event. In a particular example, an apparatus includes the SRAM storage element and control circuitry coupled to the SRAM storage element. The control circuitry may be configured to program the value to the SRAM storage element, to increase the supply voltage, and to sense the state of the SRAM storage element to determine the value programmed to the SRAM storage element prior to the power-down event.

Abstract: Embodiments disclosed herein may relate to programming a memory cell with a programming pulse that comprises a quenching period having different portions. The memory cell may have more than two possible programmed states, where each programmed state of the memory cell includes a different fraction of amorphous material. A memory element may be melted and then quenched. The fraction of amorphous material, and thus the programmed state, may be controlled by selecting one of multiple quenching periods for the programming pulse.

Abstract: Non-volatile memory devices and logic devices are fabricated using processes compatible with high dielectric constant/metal gate (HK/MG) processes for increased cell density and larger scale integration.

Abstract: Memory programming methods and memory systems are described. One example memory programming method includes first applying a first signal to a memory cell to attempt to program the memory cell to a desired state, wherein the first signal corresponds to the desired state, after the first applying, determining that the memory cell failed to place in the desired state, after the determining, second applying a second signal to the memory cell, wherein the second signal corresponds to another state which is different than the desired state, and after the second applying, third applying a third signal to the memory cell to program the memory cell to the desired state, wherein the third signal corresponds to the desired state. Additional method and apparatus are described.

Abstract: Embodiments disclosed herein may relate to programming a memory cell with a programming pulse that comprises a quenching period having different portions.