Patents by Inventor Xiaopei FANG

Xiaopei FANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11996290
    Abstract: A semiconductor structure, including a plurality of connection patterns disposed on the substrate, and a merged pattern disposed between adjacent two of the connection patterns, wherein the merged pattern includes a first outer line, a central line and a second outer line sequentially arranged along a first direction and connected with each other, and an end surface of the first outer line, an end surface of the central line and an end surface of the second outer line are misaligned along the first direction.
    Type: Grant
    Filed: March 29, 2022
    Date of Patent: May 28, 2024
    Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Gang-Yi Lin, Yu-Cheng Tung, Yi-Wang Jhan, Yifei Yan, Xiaopei Fang
  • Patent number: 11967571
    Abstract: A semiconductor structure and a method of fabricating therefor are disclosed. A second contact pad (500) is arranged lateral to a first contact pad (420) in an interconnect structure (400). As a result, during fabrication of the interconnect structure (400), the first contact pad (420) will not be present alone in a large bland area, due to the presence of the second contact pad (500). Thus, a pattern feature for the first contact pad (420) will not be over-resolved, increasing formation accuracy of the first contact pad (420) and thus guaranteeing good electrical transmission performance of the resulting interconnect structure (400).
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: April 23, 2024
    Assignee: FUJIAN JINHUA INTEGRATED CIRCUIT CO., LTD.
    Inventors: Yi-Wang Jhan, Yung-Tai Huang, Xin You, Xiaopei Fang, Yu-Cheng Tung
  • Publication number: 20230260905
    Abstract: A semiconductor structure includes a substrate, a first dielectric layer on the substrate, a second dielectric layer on the first dielectric layer, and an interconnection structure on the second dielectric layer. The interconnection structure includes at least two lateral extending portions on the second dielectric layer, and a U-shaped portion through the second dielectric layer and a portion of the first dielectric layer and connected between adjacent ends of the two lateral extending portions.
    Type: Application
    Filed: April 13, 2022
    Publication date: August 17, 2023
    Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Xiaopei FANG, Gang-Yi Lin, Congcong Wang
  • Publication number: 20230049202
    Abstract: A semiconductor structure, including a plurality of connection patterns disposed on the substrate, and a merged pattern disposed between adjacent two of the connection patterns, wherein the merged pattern includes a first outer line, a central line and a second outer line sequentially arranged along a first direction and connected with each other, and an end surface of the first outer line, an end surface of the central line and an end surface of the second outer line are misaligned along the first direction.
    Type: Application
    Filed: March 29, 2022
    Publication date: February 16, 2023
    Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Gang-Yi Lin, Yu-Cheng Tung, Yi-Wang Jhan, Yifei Yan, Xiaopei FANG
  • Publication number: 20210407936
    Abstract: A semiconductor structure and a method of fabricating therefor are disclosed. A second contact pad (500) is arranged lateral to a first contact pad (420) in an interconnect structure (400). As a result, during fabrication of the interconnect structure (400), the first contact pad (420) will not be present alone in a large bland area, due to the presence of the second contact pad (500). Thus, a pattern feature for the first contact pad (420) will not be over-resolved, increasing formation accuracy of the first contact pad (420) and thus guaranteeing good electrical transmission performance of the resulting interconnect structure (400).
    Type: Application
    Filed: March 17, 2020
    Publication date: December 30, 2021
    Inventors: Yi-Wang JHAN, Yung-Tai HUANG, Xin YOU, Xiaopei FANG, Yu-Cheng TUNG
  • Publication number: 20210272961
    Abstract: A contact structure, contact pad layout and structure, mask combination and manufacturing method thereof is provided in the present invention. Through the connection of tops of at least two contact plugs in the boundary of core region, an integrated contact with larger cross-sectional area is formed in the boundary of core region. Accordingly, the process of forming electronic components on the contact structure in the boundary of core region may be provided with sufficient process window to increase the size of electronic components in the boundary, lower contact resistance, and the electronic component with increased size in the boundary buffer the density difference of circuit patterns between the core region and the peripheral region, thereby improving optical proximity effect and ensuring the uniformity of electronic components on the contact plugs inside the boundary of core region, and avoiding the collapse of electronic components on the contact plug in the boundary.
    Type: Application
    Filed: May 14, 2021
    Publication date: September 2, 2021
    Inventors: Yu-Cheng TUNG, Yi-Wang JHAN, Yung-Tai HUANG, Xiaopei FANG, Shaoyi WU, Yi-Lei TSENG