Abstract: Memory systems are disclosed which are comprised of a two or dual layer printed circuit board. Attached to the top layer of the dual layer printed circuit board are a memory chip and a memory controller with aligned, optimistic pin outs that optimized signal integrity layouts between certain high speed pins in a single layer. A set of high speed lines, including the data lines, that do not include any vias connect certain of the pins of the memory controller to certain of the pins of the memory chip. The high speed lines are covered by a sub-PCB that includes a copper lay that extends a ground or electrical plane above the top layer of the dual layer printed circuit board.