Abstract: A system and method for efficient power analysis of an integrated circuit are described. In various implementations, a memory of a computing system stores combinatorial logic gate-level data describing functionality of a pre-silicon, gate-level representation of the integrated circuit being designed. The circuitry of the processor accesses this data, and also divides the integrated circuit into portions based on functionality. The circuitry of the processor generates first power estimation values over time for a selected first portion by executing a power estimation tool on the first portion. Afterward, the circuitry of the processor trains a data model, such as a neural network, using the generated first power estimation values. The circuitry of the processor then generates second power estimation values over time for one or more other portions by executing the data model on these portions.

Abstract: A system and method for scheduling delivery of packetized data traffic at an output port of a network node featuring a hybrid queue with a unicast subqueue and a multicast subqueue. An interleave indicator for each unicast and multicast entry in the queue is used to toggle the header type field of the hybrid queue. Upon departure, a scheduler selects between the unicast subqueue and multicast subqueue as dictated by the state of the header type field. The disclosed interleave indicator techniques add minimal overhead to the system, allowing ready scaling with increasing port densities. Further, the data structure of the multicast subqueue can be selected to optimize the system and achieve desired performance characteristics.