Abstract: An accelerated compression method and apparatus are provided. The accelerated compression apparatus includes a look-ahead memory, a string matching processing pipeline and a control circuit. According to an issue pointer, the control circuit issues sub-strings of a string to be compressed from the look-ahead memory to the string matching processing pipeline for a matching operation to obtain a matched length and a matched offset. The control circuit determines a new retiring position according to the matched length corresponding to a retire pointer. When the new retiring position exceeds an issuing position pointed by the issue pointer, the control circuit resets the string matching processing pipeline.

Abstract: A chipset with a near-data processing (NDP) engine, which uses the NDP engine to perform a command transformation and thereby to generate an input and output (I/O) command to operate a peripheral device connected to the chipset. The chipset further has a traffic control module. The chipset receives a request to operate the peripheral device, and the traffic control module directs the request to the NDP engine to be transformed into the I/O command. The NDP engine may implement a file system, or achieve acceleration of a database or may be operated to cope with a remote direct memory access packet.

Abstract: A type of substituted penta-fused hexa-heterocyclic compounds having selective inhibition for PIKfyve kinase, a pharmaceutically acceptable salt and pharmaceutically acceptable solvate thereof, a method for the preparation thereof, a pharmaceutical composition comprising the same, and use of these compounds in the manufacture of a medicament for preventing or treating a disease associated with PIKfyve in vivo, in particular in the manufacture of a medicament for preventing or treating tumor growth and metastasis.

Abstract: An accelerated compression method and apparatus are provided. The accelerated compression apparatus includes a look-ahead buffer, a string matching processing pipeline and a control circuit. The string to be compressed extracted from the data register is stored to the look-ahead buffer. P instances are issued in parallel from the look-ahead buffer in each issue cycle. When P substrings corresponding to the instances are identical to each other, one of the P instances is sent to the string matching processing pipeline for a matching operation by the control circuit, and the remaining instances of the P instances are prevent from being sent to the string matching processing pipeline.

Abstract: An accelerated compression method and apparatus are provided. The accelerated compression apparatus includes a look-ahead buffer, a string matching processing pipeline and a control circuit. A string to be compressed extracted from the data register is stored to the look-ahead buffer. P instances are issued in parallel from the look-ahead buffer. When P substrings corresponding to the P instances issued in a first issue cycle are identical, the control circuit sends a first instance and a second instance of the P instances to the string matching processing pipeline for a matching operation and does not send the remaining instances of these P instances to the string matching processing pipeline. In consecutive issue cycles after the first issue cycle, the control circuit does not send any of the P instances to the string matching processing pipeline until the P substrings corresponding to the P instances are not identical.

Abstract: The present invention relates to a compound having the following formula, or a stereoisomer thereof, a prodrug thereof, a pharmaceutically acceptable salt thereof or a pharmaceutically acceptable solvate thereof, preparation method thereof, pharmaceutical composition comprising the same and use of the compound in the manufacture of a medicament for preventing or treating tumor, wherein the substituents are as defined in the specification.

Abstract: Disclosed is a marker for observing an effect of a compound or a drug on cells in real time. The marker is: 1) an amino acid sequence shown in SEQ No. 1 and/or SEQ No. 2; or 2) an amino acid sequence having a function for observing an effect of a compound or a drug on cells in real time and having at least more than 80%, preferably more than 85%, more preferably 90%, further preferably 95%, and most preferably 99% homology with the amino acid sequence shown in SEQ No. 1 and/or SEQ No. 2.

Abstract: A fuel ball detecting method and system with a self-diagnosis function are provided. The method includes: exciting a first detecting coil and a second detecting coil of a fuel ball sensor disposed outside a pipeline; obtaining a first voltage signal U1 from the first detecting coil and a second voltage signal U2 from the second detecting coil; processing U1 and U2 by differential amplification, band pass filtering, phase sensitive detection and low pass filtering by a signal processor to obtain a fuel ball waveform signal U0; determining whether the fuel ball passes the pipeline according to U0 by a single chip microcomputer; determining whether the first and the second detecting coils, the signal processor and the single chip microcomputer work normally; outputting a result showing whether the fuel ball passes the pipeline, when the first and the second detecting coils, the signal processor and the single chip microcomputer work normally.

Abstract: A chipset with a near-data processing (NDP) engine, which uses the NDP engine to perform a command transformation and thereby to generate an input and output (I/O) command to operate a peripheral device connected to the chipset. The chipset further has a traffic control module. A Remote Direct Memory Access (RDMA) packet comes from a remote computer system and is received by the chipset to operate the peripheral device. The traffic control module directs the RDMA packet to the NDP engine to be transformed into the I/O command. The NDP engine is provided to cope with the RDMA packet.

Abstract: A processing circuit and its neural network computation method are provided. The processing circuit includes multiple processing elements (PEs), multiple auxiliary memories, a system memory, and a configuration module. The PEs perform computation processes. Each of the auxiliary memories corresponds to one of the PEs and is coupled to another two of the auxiliary memories. The system memory is coupled to all of the auxiliary memories and configured to be accessed by the PEs. The configuration module is coupled to the PEs, the auxiliary memories corresponding to the PEs, and the system memory to form a network-on-chip (NoC) structure. The configuration module statically configures computation operations of the PEs and data transmissions on the NoC structure according to a neural network computation. Accordingly, the neural network computation is optimized, and high computation performance is provided.

Abstract: The present invention relates to histone deacetylase inhibitors, and to pharmaceutical compositions comprising the compounds, useful for the treatment of ischemia-reperfusion injury and for cardioprotection.

Abstract: A direct memory access (DMA) engine and a method thereof are provided. The DMA engine controls data transmission from a source memory to a destination memory, and includes a task configuration storing module, a control module and a computing module. The task configuration storing module stores task configurations. The control module reads source data from the source memory according to the task configuration. The computing module performs a function computation on the source data from the source memory in response to the task configuration of the control module. Then, the control module outputs destination data output through the function computation to the destination memory according to the task configuration. Accordingly, on-the-fly computation is achieved during data transfer between memories.

Abstract: A microprocessor provides at least two storage areas and uses a datapath for Booth multiplication. According to a first and second field of a microinstruction, the datapath gets multiplicand number supply data from the first storage area and multiplier number supply data from the second storage area. The datapath operates according to a word length indicated in a third field of the microinstruction. The datapath gets multi-bit acquisitions for Booth multiplication from the multiplier number supply data. The datapath divides the multiplicand number supply data into multiplicand numbers according to the word length, and performs Booth multiplication on the multiplicand numbers based on the multi-bit acquisitions to get partial products. According to the word length, the datapath selects a part of the partial products to be shifted and added for generation of a plurality of products.

Abstract: A microprocessor for neural network computing having a mapping table, a microcode memory, and a microcode decoding finite-state machine (FSM) is disclosed. According to the mapping table, a macroinstruction is mapped to an address on the microcode memory. The microcode decoding FSM decodes contents which are retrieved from the microcode memory according to the address, to get microinstructions involving at least one microinstruction loop that is repeated to operate a datapath to complete the macroinstruction.

Abstract: A microprocessor with dynamically adjustable bit width is provided, which has a bit width register, a datapath, a statistical register, and a bit width adjuster. The bit width register stores at least one bit width. The datapath operates according to the bit width stored in the bit width register to acquire input operands from received data and process input operands. The statistical register collects calculation results of the datapath. The bit width adjuster adjusts the bit width stored in the bit width register based on the calculation results collected in the statistical register.

Abstract: A microprocessor with Booth multiplication, in which several acquisition registers are used. In a first word length, a first acquisition register stores an unsigned ending acquisition of a first multiplier number carried in multiplier number supply data, and a third acquisition register stores a starting acquisition of a second multiplier number carried in the multiplier number supply data. In a second word length that is longer than the first word length, a fourth acquisition register stores a middle acquisition of a third multiplier number carried in the multiplier number supply data. A partial product selection circuit is required for selection of a partial product, to get the partial product from Booth multiplication based on the third acquisition register (corresponding to the first word length) or based on the fourth acquisition register (corresponding to the second word length).

Abstract: A micro-processor circuit and a method of performing neural network operation are provided. The micro-processor circuit is suitable for performing neural network operation. The micro-processor circuit includes a parameter generation module, a compute module and a compare logic. The parameter generation module receives in parallel a plurality of input parameters and a plurality of weight parameters of the neural network operation. The parameter generation module generates in parallel a plurality of sub-output parameters according to the input parameters and the weight parameters. The compute module receives in parallel the sub-output parameters. The compute module sums the sub-output parameters to generate a summed parameter. The compare logic receives the summed parameter. The compare logic performs a comparison operation based on the summed parameter to generate a plurality of output parameters of the neural network operation.

Abstract: A micro-processor circuit and a method of performing neural network operation are provided. The micro-processor circuit is suitable for performing neural network operation. The micro-processor circuit includes a parameter generation module, a compute module and a truncation logic. The parameter generation module receives in parallel a plurality of input parameters and a plurality of weight parameters of the neural network operation. The parameter generation module generates in parallel a plurality of sub-output parameters according to the input parameters and the weight parameters. The compute module receives in parallel the sub-output parameters. The compute module sums the sub-output parameters to generate a summed parameter. The truncation logic receives the summed parameter. The truncation logic performs a truncation operation based on the summed parameter to generate a plurality of output parameters of the neural network operation.

Abstract: A microprocessor having the capability of executing a micro-instruction for series calculation is provided. The microprocessor includes an instruction decoder and an execution circuit for series calculation. The micro-instruction whose source operands correspond to an undetermined number x and a plurality of coefficients a0 to an (for x0 to xn) is decoded by the instruction decoder. Based on x and a0 to an, the execution circuit for series calculation includes at least one multiplier for calculating exponentiation values of x (e.g. xp), and includes at least one MAU (multiply-and-accumulate unit) for combining x, the exponentiation values of x, and the coefficients a0 to an for the series calculation.

Abstract: A storage device includes a memory unit, an access monitor, and a memory configurator. The memory unit includes a plurality of memory blocks. The access monitor is configured to monitor whether an access mode of the memory unit is a continuous-access mode or a random-access mode, to generate a monitor signal. The memory configurator configures, according to the monitor signal, any of the memory blocks to be either in a cache mode or a SRAM state to generate a configuration signal.