Abstract: An apparatus and method are provided for performing an index operation. The apparatus has vector processing circuitry to perform an index operation in each of a plurality of lanes of parallel processing. The index operation requires an index value opm to be multiplied by a multiplier value e to produce a multiplication result. The number of lanes of parallel processing is dependent on a specified element size, and the multiplier value is different, but known, for each lane of parallel processing. The vector processing circuitry comprises mapping circuitry to perform, within each lane, mapping operations on the index value opm in order to generate a plurality of intermediate input values. The plurality of intermediate input values are such that the addition of the plurality of intermediate input values produces the multiplication result. Within each lane the mapping operations are determined by the multiplier value used for that lane.

Abstract: The disclosure discloses a touch substrate, a method thereof for positioning a touch, and a capacitive touch screen, and the touch substrate includes a base substrate and a plurality of separate touch electrodes arranged in a single layer on the base substrate, where the touch electrodes include first touch electrodes and second touch electrodes, arranged alternately in both a first direction and a second direction, and respective first touch electrodes in each of at least one row or column of the touch electrodes are connected through one same wire, or respective second touch electrodes in each of at least one row or column of the touch electrodes are connected through one same wire.

Abstract: An apparatus and method of data processing are provided. The apparatus comprises at least two execution pipelines, one with a shorter execution latency than the other. The execution pipelines share a write port and issue circuitry of the apparatus issues decoded instructions to a selected execution pipeline. The apparatus further comprises at least one additional pipeline stage and the issue circuitry can detect a write port conflict condition in dependence on a latency indication associated with a decoded instruction which it is to issue. If the issue circuitry intends to issue the decoded instruction to the execution pipeline with the shorter execution latency then when the write port conflict condition is found the issue circuitry will cause use of at least one additional pipeline stage in addition to the target execution pipeline to avoid the write port conflict.

Abstract: Apparatuses and methods of data processing are disclosed. An apparatus comprises two data processing clusters each having multiple data processing lanes to perform single instruction multiple data (SIMD) processing. Decoded instructions are issued to at least one of the two data processing clusters. A decoded SIMD instruction specifying a vector length which is more than the width of the data processing lanes of the first data processing cluster has a first part issued to the first data processing cluster for execution. An issuance target for a second remaining part of the decoded SIMD instruction is selected in dependence on a dynamic performance condition. When the dynamic performance condition has a first state the issuance target is the first data processing cluster and when the dynamic performance condition has a second state the issuance target is the second data processing cluster.

Abstract: Apparatus comprises counter and bit-shift circuitry to provide a succession of processing stages each comprising a count operation stage and a corresponding bit-shift stage, each processing stage operating with respect to a set of contiguous n-bit groups of bit positions, where n is 1 for a first processing stage and n doubles from one processing stage in the succession of processing stages to a next processing stage in the succession of processing stages; each count operation stage being configured to generate, for a first set of alternate instances of the n-bit groups of bit positions, count values indicating a respective number of bits of a predetermined bit value in a mask data word; and each bit-shift stage being configured to generate a bit-shifted data word by bit-shifting bits of a data word to be processed, for a second set of alternate instances of the n-bit groups of bit positions complementary to the first set, by respective numbers of bit positions dependent upon the count values generated by the

Abstract: An apparatus has a processing pipeline, and first and second register files. A temporary-register-using instruction is supported which controls the pipeline to perform an operation using a temporary variable derived from an operand stored in the first register file. In response to the instruction, when a predetermined condition is not satisfied, the pipeline processes at least one register move micro-operation to transfer data from the at least one source register of the first register file to at least one newly allocated temporary register of the second register file. When the condition is satisfied, the operation can be performed using a temporary variable already stored in the temporary register of the second register file used by an earlier temporary-register-using instruction specifying the same source register for determining the temporary variable, in the absence of an intervening instruction for rewriting the source register.

Abstract: Apparatuses and methods of data processing are disclosed. An apparatus comprises two data processing clusters each having multiple data processing lanes to perform single instruction multiple data (SIMD) processing. Decoded instructions are issued to at least one of the two data processing clusters. A decoded SIMD instruction specifying a vector length which is more than the width of the data processing lanes of the first data processing cluster has a first part issued to the first data processing cluster for execution. An issuance target for a second remaining part of the decoded SIMD instruction is selected in dependence on a dynamic performance condition. When the dynamic performance condition has a first state the issuance target is the first data processing cluster and when the dynamic performance condition has a second state the issuance target is the second data processing cluster.

Abstract: An apparatus and method of data processing are provided. The apparatus comprises at least two execution pipelines, one with a shorter execution latency than the other. The execution pipelines share a write port and issue circuitry of the apparatus issues decoded instructions to a selected execution pipeline. The apparatus further comprises at least one additional pipeline stage and the issue circuitry can detect a write port conflict condition in dependence on a latency indication associated with a decoded instruction which it is to issue. If the issue circuitry intends to issue the decoded instruction to the execution pipeline with the shorter execution latency then when the write port conflict condition is found the issue circuitry will cause use of at least one additional pipeline stage in addition to the target execution pipeline to avoid the write port conflict.

Abstract: The disclosure discloses a touch substrate, a method thereof for positioning a touch, and a capacitive touch screen, and the touch substrate includes a base substrate and a plurality of separate touch electrodes arranged in a single layer on the base substrate, where the touch electrodes include first touch electrodes and second touch electrodes, arranged alternately in both a first direction and a second direction, and respective first touch electrodes in each of at least one row or column of the touch electrodes are connected through one same wire, or respective second touch electrodes in each of at least one row or column of the touch electrodes are connected through one same wire.

Abstract: A pegylated artesunate derivative, a pharmaceutical composition and uses thereof, the pegylated artesunate derivative is represented by the general formula (I): The pegylated artesunate derivative has activity comparable to that of artesunate, increased water solubility and stability, and an extended half-life in vivo.

Abstract: A pegylated artesunate derivative, a pharmaceutical composition and uses thereof, the pegylated artesunate derivative is represented by the general formula (I): The pegylated artesunate derivative has activity comparable to that of artesunate, increased water solubility and stability, and an extended half-life in vivo.

Abstract: A robot and trailer system is disclosed. The robot can have a hitch that can attach to the trailer. The hitch can he remotely controlled to release and detach the trailer from the robot. The front panel of the trailer can be rounded, for example to enable dragging over obstacles with a reduced risk of snagging or catching on the obstacle.

Abstract: An apparatus for detachably mounting a head gimbal assembly to an actuator coil assembly is described. The apparatus includes a lever pivotally connected to an upper surface of an arm of the actuator coil assembly and operable to pivot between a release position and a mount position. A capture pin extends from the lever into a mounting hole of the arm. The capture pin is substantially perpendicular to the lever and is collectively pivotable with the lever between the release position and the mount position. A spring is arranged to exert a force on the lever in a direction from the release position to the mount position. The capture pin is configured to engage the head gimbal assembly positioned on a lower mounting surface of the arm opposite the upper surface of the arm via the mounting hole and to press the head gimbal assembly into the arm when in the mount position.