Patents by Inventor Xiaoyin Yao

Xiaoyin Yao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHOD FOR CALCULATING OSCILLATION DAMPING RATIO OF POWER GRID
    Publication number: 20240192256
    Abstract: The present invention disclosed a method for calculating an oscillation damping ratio of a power grid, and relates to the field of power system operation and control. When a power system oscillates, an oscillation period, two oscillation extreme points, and an oscillation direct current component start to be detected. Then an oscillation decay time constant is calculated according to the two oscillation extreme points and the oscillation direct current component. The oscillation damping ratio is calculated through the oscillation decay time constant and the oscillation period. Compared with a conventional fitting method, the conventional fitting method cannot calculate and analyze the oscillation damping ratio in a cast that a complete oscillation waveform is not obtained. The method proposed by the present inventive patent may complete the calculation of the oscillation damping ratio in a case of obtaining 2 pieces of data, so as to accelerate the speed of calculation.
    Type: Application
    Filed: February 23, 2024
    Publication date: June 13, 2024
    Inventors: Yihui ZHANG, Libin WEN, Guangshi LIU, Qian DOU, Dongshan HUANG, Xiaoming WANG, Zhiyuan SUN, Guangling LU, Mingpo LI, Mosi LIU, Hao QIU, Xiaoyin QIU, Zhiyang YAO, Wei ZHANG
  • Circuits and methods for detection of soft errors in cache memories
    Patent number: 8397130
    Abstract: Embodiments of circuits and methods for circuits for the detection of soft errors in cache memories are described herein. Other embodiments and related methods and examples are also described herein.
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: March 12, 2013
    Assignee: Arizona Board of Regents for and on behalf of Arizona State University
    Inventors: Lawrence T. Clark, Dan W. Patterson, Xiaoyin Yao
  • Circuits and methods for dual redundant register files with error detection and correction mechanisms
    Patent number: 8397133
    Abstract: Embodiments of circuits and method for dual redundant register files with error detection and correction mechanisms are described herein. Other embodiments and related examples are also described herein.
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: March 12, 2013
    Assignee: Arizona Board of Regents for and on behalf of Arizona State University
    Inventors: Lawrence T. Clark, Dan W. Patterson, Xiaoyin Yao, David Pettit, Rahul Shringarpure
  • Circuits And Methods For Dual Redundant Register Files With Error Detection And Correction Mechanisms
    Publication number: 20100269022
    Abstract: Embodiments of circuits and method for dual redundant register files with error detection and correction mechanisms are described herein. Other embodiments and related examples are also described herein.
    Type: Application
    Filed: November 25, 2009
    Publication date: October 21, 2010
    Applicant: Arizona Board of Regents, for and behalf of Arizona State University
    Inventors: Lawrence T. Clark, Dan W. Patterson, Xiaoyin Yao, David Pettit, Rahul Shringarpure
  • Method for preventing IP address cheating in dynamica address allocation
    Publication number: 20100269018
    Abstract: Embodiments of circuits and methods for circuits for the detection of soft errors in cache memories are described herein. Other embodiments and related methods and examples are also described herein.
    Type: Application
    Filed: November 25, 2009
    Publication date: October 21, 2010
    Applicant: Arizona Board of Regents, for and behalf of Arizona State University
    Inventors: Lawrence T. Clark, Dan W. Patterson, Xiaoyin Yao