Abstract: Systems and techniques relating to voltage signal peak level detection used in sensor devices, namely in Fly-Height Sensors (FHS) devices include, according to an aspect, an integrated chip device comprising: peak detection circuitry configured to receive a voltage signal and output a peak voltage signal associated with a peak voltage level of the voltage signal, wherein the peak detection circuitry comprises: a linear loop section configured to store the peak voltage level and hold additional voltage levels of the voltage signal at an output terminal of an amplifier to a value greater than zero; and a feedback loop section configured to reduce a leakage current within the peak detection circuitry and generate a guard voltage signal usable to reduce a feedback voltage and prevent the feedback voltage from successively re-entering into the feedback loop section.

Abstract: Systems and techniques relate to current slew control circuits. According to an aspect, a system implementing the quadratic slew control aspects comprises a disk; a read/write head; and a slew control circuit coupled to the read/write head, the slew control circuit configured to: receive an input current signal, apply a slew current to the input current signal in response to a change in a power setting for the read/write head, and provide an output current signal that is adjusted to a quadratic current slew based on the applied slew current, the output current signal generating an output voltage characterized by a linear slew and controlling a movement of the read/write head over the disk.

Abstract: A method for pre-amplifying an input voltage signal to a pre-amplified voltage signal. The method includes receiving the input voltage signal; obtaining a high-pass filtered voltage signal by applying a high-pass filter to the input voltage signal; processing the high-pass filtered voltage signal to a current signal that corresponds to the high-pass filtered voltage signal; transmitting the current signal through a differential transmission line; converting the transmitted current signal to a converted voltage signal that corresponds to the high-pass filtered voltage signal; and outputting the converted voltage signal as the pre-amplified voltage signal. An integrated circuit chip implementing the method is also disclosed.

Abstract: Power-on reset circuits and methods for providing a power-on reset signal are provided. A first branch is configured to receive the power supply voltage. The first branch comprises a first current generator configured to generate a first current having a positive relationship with a power supply voltage. A second branch receives the power supply voltage and comprises a second current generator that is configured to generate a second current. A relationship between the first and second currents indicates whether the power supply voltage exceeds a threshold voltage of the power-on reset circuit. A current comparator circuit compares the first current to the second current and generates an output based on the comparison. The power-on reset signal is asserted when the output indicates that the second current is greater than the first current.

Abstract: A system including transmission lines, read elements, and differential amplifiers. The read elements are connected in series. Each of the read elements is connected to a respective pair of the transmission lines. The differential amplifiers are connected respectively to the read elements via the transmission lines. The differential amplifiers are configured to amplify differential signals received from the respective pairs of the transmission lines.

Abstract: A system including a first transmission line, a second transmission line, a first element, a second element and a differential amplifier. The first element is configured to read a storage media to generate a read signal, where the first element is connected to the first transmission line. The second element is configured to detect interference and generate an interference signal, where the second element is connected to the second transmission line. The differential amplifier includes a first input and a second input, where the first input of the differential amplifier is connected to a the first transmission line and receives the read signal, and where the second input of the differential amplifier is connected to the second transmission line and receives the interference signal.

Abstract: A system including transmission lines, read elements, and differential amplifiers. The read elements are connected in series. Each of the read elements is connected to a respective pair of the transmission lines. The differential amplifiers are connected respectively to the read elements via the transmission lines. The differential amplifiers are configured to amplify differential signals received from the respective pairs of the transmission lines.

Abstract: A system including a first transmission line, a second transmission line, a first element, a second element and a differential amplifier. The first element is configured to read a storage media to generate a read signal, where the first element is connected to the first transmission line. The second element is configured to detect interference and generate an interference signal, where the second element is connected to the second transmission line. The differential amplifier includes a first input and a second input, where the first input of the differential amplifier is connected to a the first transmission line and receives the read signal, and where the second input of the differential amplifier is connected to the second transmission line and receives the interference signal.

Abstract: Drive circuitry for driving a load through a connection to a transmission line, such as for driving the write head of a hard disk drive. A hybrid termination is provided for termination at the connection to the transmission line. The termination is hybrid since there is both an in-series and an in-parallel component to the termination resistance. In addition, in embodiments where there is matched termination of the transmission line during a boost period of driving the load, the termination is hybrid since the termination is switched between a boost period of a write operation, and a steady state period of the write operation.

Abstract: A circuit comprises first and second buffers, and an output buffer. The first buffer receives an input signal and provides a first buffer output signal on a first lead. The second buffer receives the input signal and provides a second buffer output signal on a second output lead. The output buffer has a first input lead coupled to the first output lead and AC coupled to the second output lead. The AC coupling communicates timing information from the second buffer to the output buffer. The first buffer applies sufficient voltage to control the first input lead of the output buffer under DC conditions.

Abstract: A driver for driving a load over a transmission line, such as driving the magnetic head of a hard disk drive. The driver includes a signal switch for switching the signal to the load during a signal period, and a boost switch for boosting the signal during a boost period, so as to decrease rise time of the signal at the load by deliberately injecting an overshoot. A switchable protection device protects the signal switch and the boost switch. The protection device includes a reflection-suppression switch which is pulsed during a time corresponding to the expected return of a reflection corresponding to the overshoot signal, so as to force the protection device into saturation mode. Since the protection device is in the saturation mode during the return reflection of the boost signal, the returned reflection sees a matched impedance and thus reduces a re-reflection back to the load.

Abstract: A circuit is adapted to activate a writer head of a data storage media drive during both the boost periods as well as the steady state periods. The current supplied to the writer head during the boost periods exceeds the steady state current and flows between positive and negative voltage supplies so as to provide the required magnetic flux change in the inductor disposed in the write head. During the steady state periods, a switch circuit is turned on to provide a second current path across the writer head. During the steady state periods, the current flows between the positive voltage supply and the ground to reduce power consumption. The switch circuit is turned off during the boost periods.

Abstract: A circuit is adapted to activate a writer head of a data storage media drive during both the boost periods as well as the steady state periods. The current supplied to the writer head during the boost periods exceeds the steady state current and flows between positive and negative voltage supplies so as to provide the required magnetic flux change in the inductor disposed in the write head. During the steady state periods, a switch circuit is turned on to provide a second current path across the writer head. During the steady state periods, the current flows between the positive voltage supply and the ground to reduce power consumption. The switch circuit is turned off during the boost periods.