Patents by Inventor Xin Hua
Xin Hua has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11961046Abstract: A computing device includes a processor and a medium storing instructions. The instructions are executable by the processor to: in response to a receipt of an electronic request comprising one or more structured data fields and one or more unstructured data fields, identify a set of previous electronic requests using the one or more structured data fields of the received electronic request; train a probabilistic classification model using at least one structured data field of the identified set of previous electronic requests; execute the trained probabilistic classification model using the one or more unstructured data fields of the received electronic request; and automatically select a request handler using an output of the executed probabilistic classification model.Type: GrantFiled: May 22, 2018Date of Patent: April 16, 2024Assignee: Micro Focus LLCInventors: Zhu Jing Wu, Xin-Yu Wang, Jin Wang, Chun-Hua Li, Zhen Cui
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Publication number: 20240082302Abstract: The present invention includes compositions and methods for treating AML utilizing bispecific CARs. In certain aspects, the invention includes a bispecific split CAR which binds CD13 and TIM-3 on AML cells. In one aspect, the invention provides a bispecific chimeric antigen receptor (CAR) comprising a first antigen binding domain capable of binding CD13, a first intracellular domain, a second antigen binding domain capable of binding TIM-3, a transmembrane domain, and a second intracellular domain.Type: ApplicationFiled: October 9, 2020Publication date: March 14, 2024Inventors: Xianxin HUA, Xin HE, Xuyao ZHANG
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Publication number: 20240088103Abstract: Various embodiments of the present disclosure are directed towards a three-dimensional (3D) trench capacitor, as well as methods for forming the same. In some embodiments, a first substrate overlies a second substrate so a front side of the first substrate faces a front side of the second substrate. A first trench capacitor and a second trench capacitor extend respectively into the front sides of the first and second substrates. A plurality of wires and a plurality of vias are stacked between and electrically coupled to the first and second trench capacitors. A first through substrate via (TSV) extends through the first substrate from a back side of the first substrate, and the wires and the vias electrically couple the first TSV to the first and second trench capacitors. The first and second trench capacitors and the electrical coupling therebetween collectively define the 3D trench capacitor.Type: ApplicationFiled: November 17, 2023Publication date: March 14, 2024Inventors: Xin-Hua Huang, Chung-Yi Yu, Yeong-Jyh Lin, Rei-Lin Chu
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Publication number: 20240087879Abstract: A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.Type: ApplicationFiled: November 14, 2023Publication date: March 14, 2024Inventors: Xin-Hua Huang, Ping-Yin Liu, Hung-Hua Lin, Hsun-Chung Kuang, Yuan-Chih Hsieh, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
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Publication number: 20240074773Abstract: A thrombus removal apparatus, comprising a body portion (1) and a distal portion (2).Type: ApplicationFiled: January 14, 2022Publication date: March 7, 2024Inventors: Brendan CUNNIFFE, Xin HUA, Quan SHEN
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Patent number: 11862612Abstract: Various embodiments of the present disclosure are directed towards a three-dimensional (3D) trench capacitor, as well as methods for forming the same. In some embodiments, a first substrate overlies a second substrate so a front side of the first substrate faces a front side of the second substrate. A first trench capacitor and a second trench capacitor extend respectively into the front sides of the first and second substrates. A plurality of wires and a plurality of vias are stacked between and electrically coupled to the first and second trench capacitors. A first through substrate via (TSV) extends through the first substrate from a back side of the first substrate, and the wires and the vias electrically couple the first TSV to the first and second trench capacitors. The first and second trench capacitors and the electrical coupling therebetween collectively define the 3D trench capacitor.Type: GrantFiled: December 20, 2021Date of Patent: January 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Xin-Hua Huang, Chung-Yi Yu, Yeong-Jyh Lin, Rei-Lin Chu
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Patent number: 11854795Abstract: A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.Type: GrantFiled: March 21, 2022Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Xin-Hua Huang, Ping-Yin Liu, Hung-Hua Lin, Hsun-Chung Kuang, Yuan-Chih Hsieh, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
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Patent number: 11854999Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes bonding structure arranged directly between a first substrate and a second substrate. The first substrate includes a first transparent material and a first alignment mark. The first alignment mark is arranged on an outer region of the first substrate and also includes the first transparent material. The first alignment mark is defined by surfaces of the first substrate that are arranged between an uppermost surface of the first substrate and a lowermost surface of the first substrate. The second substrate includes a second alignment mark on an outer region of the second substrate. The second alignment mark directly underlies the first alignment mark, and the bonding structure is arranged directly between the first alignment mark and the second alignment mark.Type: GrantFiled: August 4, 2022Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Xin-Hua Huang, Ping-Yin Liu
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Patent number: 11851318Abstract: A microelectromechanical system device includes a substrate, a dielectric layer, an electrode, a surface modification layer and a membrane. The dielectric layer is formed on the substrate, and is formed with a cavity that is defined by a cavity-defining wall. The electrode is formed in the dielectric layer. The surface modification layer covers the cavity-defining wall, and has a plurality of hydrophobic end groups. The membrane is connected to the dielectric layer, and seals the cavity. The membrane is movable toward or away from the electrode. A method for making a microelectromechanical system device is also provided.Type: GrantFiled: April 22, 2021Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-Chuan Teng, Ching-Kai Shen, Jung-Kuo Tu, Wei-Cheng Shen, Xin-Hua Huang, Wei-Chu Lin
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Patent number: 11845294Abstract: Disclosed is a keyboard for an information handling system. The keyboard includes a top cover comprising a polyester and a plurality of jute fibers, a keycap assembly comprising one or more keycaps, and a bottom cover comprising a first polylactic acid (PLA) and a post-consumer resin (PCR). The keycap assembly can be positioned between the top cover and the bottom cover, and the top cover can include one or more openings keycap assembly keycaps to protrude through.Type: GrantFiled: September 10, 2021Date of Patent: December 19, 2023Assignee: Dell Products L.P.Inventors: Hin Loong Wong, Xin Hua Tian, Peng Lip Goh, Deeder M. Aurongzeb
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Publication number: 20230371354Abstract: The present disclosure relates to a processing tool that includes a first wafer-mounting frame and a second wafer-mounting frame. The first wafer-mounting frame is configured to retain a target wafer. The second wafer-mounting frame is configured to retain a masking wafer. The masking wafer includes a mask pattern made up of a number of openings passing through the masking wafer to correspond to a predetermined deposition pattern to be formed on the target wafer. A deposition chamber is configured to receive the first and second wafer-mounting frames, when the first and second wafer-mounting frames are clamped together to retain the target wafer and the masking wafer. The deposition chamber includes a material deposition source configured to deposit material from the material deposition source through the number of openings in the mask pattern to form the material in the predetermined deposition pattern on the target wafer.Type: ApplicationFiled: July 28, 2023Publication date: November 16, 2023Inventors: Ping-Yin Liu, Chia-Shiung Tsai, Xin-Hua Huang, Yu-Hsing Chang, Yeong-Jyh Lin
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Patent number: 11818944Abstract: The present disclosure relates to a processing tool that includes a first wafer-mounting frame and a second wafer-mounting frame. The first wafer-mounting frame is configured to retain a target wafer. The second wafer-mounting frame is configured to retain a masking wafer. The masking wafer includes a mask pattern made up of a number of openings passing through the masking wafer to correspond to a predetermined deposition pattern to be formed on the target wafer. A deposition chamber is configured to receive the first and second wafer-mounting frames, when the first and second wafer-mounting frames are clamped together to retain the target wafer and the masking wafer. The deposition chamber includes a material deposition source configured to deposit material from the material deposition source through the number of openings in the mask pattern to form the material in the predetermined deposition pattern on the target wafer.Type: GrantFiled: March 2, 2020Date of Patent: November 14, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ping-Yin Liu, Chia-Shiung Tsai, Xin-Hua Huang, Yu-Hsing Chang, Yeong-Jyh Lin
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Publication number: 20230357355Abstract: Related are a CSPG4-targeting humanized chimeric antigen receptor and applications thereof, comprising a humanized anti-CSPG4 binding domain, a hinge region, a transmembrane domain, and a signal transduction domain. The anti-CSPG4 binding domain comprises an anti-CSPG4 antibody or antigen binding part. Related are an immune effector cell expressing the CSPG4-targeting humanized chimeric antigen receptor and applications of the cell.Type: ApplicationFiled: September 23, 2021Publication date: November 9, 2023Applicant: BOYUAN RUNSHENG PHARMA (HANGZHOU) CO., LTD.Inventors: Chuang SUN, Xin-Hua FENG, Bin ZHAO
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Patent number: 11779066Abstract: A gown is disclosed with an opening in the back extending from the neck area to the bottom creating 2 panels. At least one elastic/flexible/stretchable strap is provided in the neck area of the gown. Each flexible strap has one end attached to each of the 2 panels of the open gown. The gown is designed for the first panel to extend over the second panel and can be weighted to minimize any movement of the first panel away from the second panel. In another embodiment a portion of the first panel extends to the user's side or front area and secured to the side or front of the gown.Type: GrantFiled: August 27, 2020Date of Patent: October 10, 2023Assignee: MEDICOM GROUP INC.Inventors: Nektaria Markoglou, Xin Hua Li
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Publication number: 20230285040Abstract: There is provided a clot retrieval device, comprising: a rotator body formed of a plurality of first longitudinal struts, wherein the first longitudinal struts are fixed only at a proximal end and a distal end, and the rotator body is in an expanded configuration when it is in a free state, and can be in a collapsed configuration when it is inserted into a catheter; and a distal body connected to the distal end of the rotator body, the distal body is in an expanded configuration when it is in a free state, and can be in a collapsed configuration when it is inserted into a catheter; wherein at least a portion of each of the first longitudinal struts makes both radial expansion and circumferential rotation during a deployment phase of the rotator body from the collapsed configuration to the expanded configuration.Type: ApplicationFiled: July 26, 2021Publication date: September 14, 2023Inventors: Brendan CUNNIFFE, Xin HUA, Quan SHEN
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Patent number: 11742321Abstract: The present disclosure, in some embodiments, relates to a workpiece bonding apparatus. The workpieces bonding apparatus includes a first substrate holder having a first surface configured to receive a first workpiece, and a second substrate holder having a second surface configured to receive a second workpiece. A vacuum apparatus is positioned between the first substrate holder and the second substrate holder and is configured to selectively induce a vacuum between the first surface and the second surface. The vacuum is configured to attract the first surface and the second surface toward one another.Type: GrantFiled: May 13, 2021Date of Patent: August 29, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Xin-Hua Huang, Kuan-Liang Liu, Kuo Liang Lu, Ping-Yin Liu
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Publication number: 20230253334Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a semiconductor device that is inverted and that overlies a dielectric region inset into a top of a semiconductor substrate. An interconnect structure overlies the semiconductor substrate and the dielectric region and further comprises an intermetal dielectric (IMD) layer. The IMD layer is bonded to the top of the semiconductor substrate and accommodates a pad. A semiconductor layer overlies the interconnect structure, and the semiconductor device is in the semiconductor layer, between the semiconductor layer and the interconnect structure. The semiconductor device comprises a first source/drain electrode overlying the dielectric region and further overlying and electrically coupled to the pad. The dielectric region reduces substrate capacitance to decrease substrate power loss and may, for example, be a cavity or a dielectric layer. A contact extends through the semiconductor layer to the pad.Type: ApplicationFiled: April 18, 2023Publication date: August 10, 2023Inventors: Xin-Hua Huang, Chung-Yi Yu, Kuei-Ming Chen
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Patent number: 11721637Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes bonding structure arranged directly between a first substrate and a second substrate. The first substrate includes a first transparent material and a first alignment mark. The first alignment mark is arranged on an outer region of the first substrate and also includes the first transparent material. The first alignment mark is defined by surfaces of the first substrate that are arranged between an uppermost surface of the first substrate and a lowermost surface of the first substrate. The second substrate includes a second alignment mark on an outer region of the second substrate. The second alignment mark directly underlies the first alignment mark, and the bonding structure is arranged directly between the first alignment mark and the second alignment mark.Type: GrantFiled: May 27, 2020Date of Patent: August 8, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Xin-Hua Huang, Ping-Yin Liu
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Publication number: 20230238268Abstract: In some embodiments, the present disclosure relates to a method that includes aligned a first wafer with a second wafer. The second wafer is spaced apart from the first wafer. The first wafer is arranged on a first electrostatic chuck (ESC). The first ESC has electrostatic contacts that are configured to attract the first wafer to the first ESC. Further, the second wafer is brought toward the first wafer to directly contact the first wafer at an inter-wafer interface. The inter-wafer interface is localized to a center of the first wafer. The second wafer is deformed to gradually expand the inter-wafer interface from the center of the first wafer toward an edge of the first wafer. The electrostatic contacts of the first ESC are turned OFF such that the first and second wafers are bonded to one another by the inter-wafer interface.Type: ApplicationFiled: March 29, 2023Publication date: July 27, 2023Inventors: Xin-Hua Huang, Ping-Yin Liu, Chang-Chen Tsao
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Publication number: 20230212774Abstract: Disclosed is a post-plating treatment method for a one-step brass-electroplated steel wire, comprising the following steps: electroplating the surface of the steel wire with a brass alloy; immediately washing the electroplated steel wire with cold water, removing residues from the surface of the steel wire, and blow-drying the steel wire with cold air; immersing the blow-dried steel wire in a water-based coating solution; and taking the immersed steel wire out, blow-drying the steel wire with natural air, and taking the steel wire up. The water-based coating solution comprises a polyoxyethylene organic salt, sodium hypophosphite and the balance of pure water, the polyoxyethylene organic salt comprising a salt of alkyl polyoxyethylene ether phosphate and polyoxyethylene alkylamine.Type: ApplicationFiled: May 28, 2021Publication date: July 6, 2023Applicant: Jiangsu Xingda Steel Tyre Cord Co., Ltd.Inventors: Xiang LIU, Na LI, Weigang MIAO, Lili YAO, Xianghui LIU, Xin HUA, Yubo WEI, Chenlu ZHU