Abstract: A semiconductor device includes a through-silicon via (TSV) in a TSV zone in a substrate and the TSV extends through the substrate; an ESD cell proximal to a first end of the TSV and in contact with the TSV zone, the ESD cell including a set of diodes electrically connected in parallel to each other; an antenna pad electrically connected to a second end of the TSV; and an antenna electrically connected to the antenna pad and extending in a first direction, the first direction is parallel to a major axis of the TSV. The semiconductor device includes a conductive pillar extending parallel to the TSV at a same side of the substrate as the antenna pad, wherein a first end of the conductive pillar electrically connects to the antenna pad, and a second end of the conductive pillar electrically connects to the set of diodes of the ESD cell.

Abstract: A method of manufacturing an IC structure includes configuring each of an n-well and a p-well in a first IC die to have a first portion extending in a first direction and second and third portions extending from the first portion in a second direction perpendicular to the first direction, and forming IC devices including a first pickup structure electrically connected to the n-well and a second pickup structure electrically connected to the p-well. Forming the IC devices includes forming a PMOS transistor in the second or third portion of the n-well and forming an NMOS transistor in the second or third portion of the p-well.

Abstract: An integrated circuit includes a first terminal-conductor, a second terminal-conductor, and a gate-conductor between the first terminal-conductor and the second terminal-conductor. The first terminal-conductor intersects both an active-region structure and a power rail. The second terminal-conductor intersects the active-region structure without intersecting the power rail. The gate-conductor intersects the active-region structure and is adjacent to the first terminal-conductor and the second terminal-conductor. A first width of the first terminal-conductor is larger than a second width of the second terminal-conductor by a predetermined amount.

Abstract: An integrated circuit (IC) structure includes a continuous well including first through third well portions. The continuous well is one of an n-well or a p-well, the first well portion extends in a first direction, the second well portion extends from the first well portion in a second direction perpendicular to the first direction, and the third well portion extends from the first well portion in the second direction parallel to the second well portion.

Abstract: A method of manufacturing an ECO base cell includes forming first and second active areas on opposite sides of, and having corresponding long axes arranged parallel to, a first axis of symmetry; forming non-overlapping first, second and third conductive structures having long axes in a second direction perpendicular to the first direction and parallel to a second axis of symmetry, each of the first, second and third conductive structures to correspondingly overlap the first and second active areas, the first conductive structure being between the second and third conductive structures; removing material from central regions of the second and third conductive structures; and forming a fourth conductive structure being over the central regions of the second and third conductive structures and occupying an area which substantially overlaps a first segment of the first conductive structure and a first segment of one of the second and third conductive structures.

Abstract: A method of making an integrated circuit includes dividing, in a first layer of an integrated circuit layout, a first arrangement of metal lines into a first set of metal lines and a second set of metal lines, wherein the first set of metal lines is between the second set of metal lines and a periphery of the integrated circuit layout, wherein the first arrangement of metal lines is configured to electrically connect to a plurality of contacts connected to a second layer of the integrated circuit layout after a manufacturing process. The method further includes adjusting a metal line perimeter of at least one metal line in the second set of metal lines to make a second arrangement of metal lines, wherein each adjusted metal line perimeter is separated from contacts in the second layer of the integrated circuit layout by at least a check distance.

Abstract: A method of manufacturing an ECO base cell includes forming first and second active areas on opposite sides of, and having corresponding long axes arranged parallel to, a first axis of symmetry; forming non-overlapping first, second and third conductive structures having long axes in a second direction perpendicular to the first direction and parallel to a second axis of symmetry, each of the first, second and third conductive structures to correspondingly overlap the first and second active areas, the first conductive structure being between the second and third conductive structures; removing material from central regions of the second and third conductive structures; and forming a fourth conductive structure being over the central regions of the second and third conductive structures and occupying an area which substantially overlaps a first segment of the first conductive structure and a first segment of one of the second and third conductive structures.

Abstract: An integrated circuit includes an array of first-type active-region structures and an array of second-type active-region structures extending in a first direction between a first vertical zone-boundary of a first keep-out zone and the second vertical zone-boundary of a second keep-out zone. The integrated circuit also includes an array of first-side boundary cells aligned with the first vertical zone-boundary and an array of second-side boundary cells aligned with the second vertical zone-boundary. In the array of first-side boundary cells, a first-side boundary cell has a first ESD protection circuit and a pick-up region. In the array of second-side boundary cells, a second-side boundary cell has a second ESD protection circuit.

Abstract: A method includes steps of dividing a first arrangement of metal lines in a circuit layout into two sets of metal lines, a first set of metal lines in a peripheral area, and a second set of metal lines in a center area. The arrangement of metal lines is configured to electrically connect to contacts of a second layer of the circuit layout. The method includes adjusting a metal line perimeter of at least one metal line in the center area to make a second arrangement of metal lines, where each adjusted metal line perimeter is separated from contacts in the second layer of the integrated circuit layout by at least a check distance.

Abstract: Standard cell libraries include one or more standard cells and one or more corresponding standard cell variations. The one or more standard cell variations are different from their one or more standard cells in terms of geometric shapes, locations of the geometric shapes, and/or interconnections between the geometric shapes. The exemplary systems and methods described herein selectively choose from among the one or more standard cells and/or the one or more standard cell variations to form an electronic architectural design for an electronic device. In some situations, some of the one or more standard cells are unable to satisfy one or more electronic design constraints imposed by a semiconductor foundry and/or semiconductor technology node when placed onto the electronic device design real estate. In these situations, the one or more standard cell variations corresponding to these standard cells are placed onto the electronic device design real estate.

Abstract: An integrated circuit (IC) device includes a first substrate, a through substrate via (TSV) in the first substrate, and a first antenna effect protection circuit over the first substrate and electrically coupled to the TSV. The first antenna effect protection circuit includes at least one first transistor of a first type, and at least one second transistor of a second type different from the first type. A gate terminal, a first terminal and a second terminal of each of the at least one first transistor and the at least one second transistor are electrically coupled together, and to the TSV.

Abstract: A semiconductor device includes a through-silicon via (TSV) in a TSV zone in a substrate and the TSV extends through the substrate; an ESD cell proximal to a first end of the TSV and in contact with the TSV zone, the ESD cell including a set of diodes electrically connected in parallel to each other; an antenna pad electrically connected to a second end of the TSV; and an antenna electrically connected to the antenna pad and extending in a first direction, the first direction is parallel to a major axis of the TSV. The semiconductor device includes a conductive pillar extending parallel to the TSV at a same side of the substrate as the antenna pad, wherein a first end of the conductive pillar electrically connects to the antenna pad, and a second end of the conductive pillar electrically connects to the set of diodes of the ESD cell.

Abstract: An integrated circuit (IC) structure includes a continuous well including first through third well portions. The continuous well is one of an n-well or a p-well, the first well portion extends in a first direction, the second well portion extends from the first well portion in a second direction perpendicular to the first direction, and the third well portion extends from the first well portion in the second direction parallel to the second well portion.

Abstract: A method of generating a layout diagram of a semiconductor device includes populating a conductive layer M(h) with segment patterns representing corresponding conductive segments in the semiconductor device. The segment patterns including first and second power grid (PG) patterns and first routing patterns, where h is an integer and h?1. Arranging long axes of the first and second PG patterns and the first routing patterns to extend in a first direction. Arranging the first and second PG patterns to be separated, relative to a second direction, by a PG gap having a midpoint. The second direction being substantially perpendicular to the first direction. Distributing the first routing patterns between the first and second PG patterns and substantially uniformly in the second direction with respect to the midpoint of the PG gap.

Abstract: Standard cell libraries include one or more standard cells and one or more corresponding standard cell variations. The one or more standard cell variations are different from their one or more standard cells in terms of geometric shapes, locations of the geometric shapes, and/or interconnections between the geometric shapes. The exemplary systems and methods described herein selectively choose from among the one or more standard cells and/or the one or more standard cell variations to form an electronic architectural design for an electronic device. In some situations, some of the one or more standard cells are unable to satisfy one or more electronic design constraints imposed by a semiconductor foundry and/or semiconductor technology node when placed onto the electronic device design real estate. In these situations, the one or more standard cell variations corresponding to these standard cells are placed onto the electronic device design real estate.

Abstract: Standard cell libraries include one or more standard cells and one or more corresponding standard cell variations. The one or more standard cell variations are different from their one or more standard cells in terms of geometric shapes, locations of the geometric shapes, and/or interconnections between the geometric shapes. The exemplary systems and methods described herein selectively choose from among the one or more standard cells and/or the one or more standard cell variations to form an electronic architectural design for an electronic device. In some situations, some of the one or more standard cells are unable to satisfy one or more electronic design constraints imposed by a semiconductor foundry and/or semiconductor technology node when placed onto the electronic device design real estate. In these situations, the one or more standard cell variations corresponding to these standard cells are placed onto the electronic device design real estate.

Abstract: A semiconductor device includes: a conductive layer M(h) including first and second power grid (PG) segments and first routing segments which are conductive, where h is an integer and h?1; long axes of the first and second PG segments and the first routing segments extending in a first direction; the first and second PG segments being separated in a second direction by a PG gap having a midpoint, the second direction being substantially perpendicular to the first direction. The first routing segments are distributed: between the first and second PG segments; and substantially uniformly in the second direction with respect to the midpoint of the PG gap.

Abstract: A method includes steps of dividing a first arrangement of metal lines in a circuit layout into two sets of metal lines, a first set of metal lines in a peripheral area, and a second set of metal lines in a center area. The arrangement of metal lines is configured to electrically connect to contacts of a second layer of the circuit layout. The method includes adjusting a metal line perimeter of at least one metal line in the center area to make a second arrangement of metal lines, where each adjusted metal line perimeter is separated from contacts in the second layer of the integrated circuit layout by at least a check distance.

Abstract: A method of manufacturing an ECO base cell includes forming first and second active areas on opposite sides of, and having corresponding long axes arranged parallel to, a first axis of symmetry; forming non-overlapping first, second and third conductive structures having long axes in a second direction perpendicular to the first direction and parallel to a second axis of symmetry, each of the first, second and third conductive structures to correspondingly overlap the first and second active areas, the first conductive structure being between the second and third conductive structures; removing material from central regions of the second and third conductive structures; and forming a fourth conductive structure being over the central regions of the second and third conductive structures and occupying an area which substantially overlaps a first segment of the first conductive structure and a first segment of one of the second and third conductive structures.

Abstract: A system (including a processor and memory with computer program code) configured to execute a method which includes generating a layout diagram including: generating first and second active area patterns on opposite sides of (and having long axes parallel to) a first symmetry axis; generating non-overlapping first, second and third conductive patterns (having long axes perpendicular to the first symmetry axis) which overlap the first and second active area patterns; centering the first conductive pattern between the second and third conductive patterns; generating a first cut-pattern for, and which overlaps, central regions of the second and third conductive patterns; centering the first cut-pattern relative to the first symmetry axis; generating a fourth conductive pattern over an area bounded by the first cut-pattern; and expanding the fourth conductive pattern to substantially overlap a portion of the first conductive pattern and a portion of the second or third conductive patterns.