Abstract: The present disclosure relates to image rendering methods apparatuses, and electronic devices. One example method includes obtaining, by a central processing unit (CPU), an image command stream used to render an image frame, comparing the image command stream with a previous image command stream, and, when a same drawing command exists in the two image command streams, instructing a graphics processing unit (GPU) to render the image frame based on a previously generated drawing target.

Abstract: The present disclosure relates to image rendering methods, apparatus, and electronic devices. One example method includes obtaining, by a central processing unit (CPU), an image command stream used to render an image frame, comparing the image command stream with a previous image command stream and, when a same drawing command exists in the two image command streams, instructing a graphics processing unit (GPU) to render the image frame based on a previously generated drawing target.

Abstract: The present disclosure relates to a frequency modulation device, a switching power supply and a frequency modulation method thereof. The device includes: a waveform generation unit (10) configured to generate a periodic signal required for performing frequency modulation on a clock signal of a switching power supply to be controlled; a frequency modulation unit (20) configured to perform voltage-current conversion and arithmetic processing based on the periodic signal to obtain a frequency modulation current required for performing the frequency modulation on the clock signal of the switching power supply to be controlled; and an RC oscillation unit (30) configured to perform RC oscillation processing based on the frequency modulation current to obtain a frequency oscillation signal as the clock signal of the switching power supply to be controlled.

Abstract: The present disclosure relates to a frequency modulation device, a switching power supply and a frequency modulation method thereof. The device includes: a waveform generation unit (10) configured to generate a periodic signal required for performing frequency modulation on a clock signal of a switching power supply to be controlled; a frequency modulation unit (20) configured to perform voltage-current conversion and arithmetic processing based on the periodic signal to obtain a frequency modulation current required for performing the frequency modulation on the clock signal of the switching power supply to be controlled; and an RC oscillation unit (30) configured to perform RC oscillation processing based on the frequency modulation current to obtain a frequency oscillation signal as the clock signal of the switching power supply to be controlled.

Abstract: An image rendering method and apparatus, an electronic device, and the like are provided, and may be applied to the terminal field. The method includes: obtaining, by a central processing unit CPU, an image command stream used to render an image frame, and comparing the image command stream with a previous image command stream; and when a same drawing command exists in the two image command streams, instructing a graphics processing unit GPU to render the image frame based on a previously generated drawing target. In other words, the GPU may reuse a drawing target of a same drawing command in different image frames, thereby reducing a process of generating the drawing target, and further reducing load of the GPU.

Abstract: Disclosed is a reference voltage circuit with low temperature drift, including a first voltage unit, a second voltage unit and a K times' amplification unit. The first voltage unit is configured to generate a first voltage, with a first end thereof being grounded. The K times' amplification unit is configured to amplify the first voltage by K times, with a first end thereof being connected to a second end of the first voltage unit, and with a second end thereof being connected to a first end of the second voltage unit, wherein K is a constant greater than zero. The second voltage unit is configured to generate a second voltage, with the first end thereof being connected to a current source circuit, and a second end thereof being connected to a third end of the first voltage unit to serve as an output end of a reference voltage (VREF).

Abstract: The embodiments of the present disclosure relate to a technical field of home electrical appliances, and particularly to methods, apparatus, systems, and electronic devices for voice controlling a smart home electrical appliance. The method includes: acquiring speech information of a user; performing a recognition on the speech information to acquire a control command; determining a target home electrical appliance according to the control command, and transmitting the control command to the target home electrical appliance; and acquiring a first execution result sent back from the target home electrical appliance, wherein the first execution result represents a state of the target home electrical appliance.

Abstract: Disclosed are a clock compensation circuit, a clock circuit and a microcontroller. The clock compensation circuit may include: a detection circuit, configured to detect a capacitance control parameter capable of affecting a clock frequency output by a clock circuit; and a control unit, connected with the detection circuit, and configured to adjust a capacitance value of a target capacitor in the clock circuit according to the capacitance control parameter detected by the detection circuit, so as to change the clock frequency output by the clock circuit. With the clock compensation circuit, the clock circuit and the microcontroller, the problem of large fluctuation of a clock frequency output by a clock circuit in the related art is solved.

Abstract: Disclosed is a reference voltage circuit with low temperature drift, including a first voltage unit, a second voltage unit and a K times' amplification unit. The first voltage unit is configured to generate a first voltage, with a first end thereof being grounded. The K times' amplification unit is configured to amplify the first voltage by K times, with a first end thereof being connected to a second end of the first voltage unit, and with a second end thereof being connected to a first end of the second voltage unit, wherein K is a constant greater than zero. The second voltage unit is configured to generate a second voltage, with the first end thereof being connected to a current source circuit, and a second end thereof being connected to a third end of the first voltage unit to serve as an output end of a reference voltage (VREF).

Abstract: Disclosed are a clock compensation circuit, a clock circuit and a microcontroller. The clock compensation circuit may include: a detection circuit, configured to detect a capacitance control parameter capable of affecting a clock frequency output by a clock circuit; and a control unit, connected with the detection circuit, and configured to adjust a capacitance value of a target capacitor in the clock circuit according to the capacitance control parameter detected by the detection circuit, so as to change the clock frequency output by the clock circuit. With the clock compensation circuit, the clock circuit and the microcontroller, the problem of large fluctuation of a clock frequency output by a clock circuit in the related art is solved.

Abstract: A display device is provided. The display device includes a transmitter, a plurality of first receivers, a plurality of second receiver modules, and a plurality of LED driver groups. The transmitter transmits at least one of a configuration data packet and an image data packet. Each of the configuration and image data packets includes a set of field information. At least one first receiver is coupled to the transmitter. Each of the plurality of second receiver modules is coupled to at least one of first receivers. Each of the plurality of second receiver modules includes a plurality of second receivers. Each of the second receivers reads the set of field information so as to determine whether the set of field information is designated thereto. Each of the plurality of LED driver groups is coupled to the at least one of the second receivers. Each of the plurality of LED driver groups includes a plurality of LED drivers.

Abstract: A display device is provided. The display device includes a transmitter, a plurality of first receivers, a plurality of second receiver modules, and a plurality of LED driver groups. The transmitter transmits at least one of a configuration data packet and an image data packet. Each of the configuration and image data packets includes a set of field information. At least one first receiver is coupled to the transmitter. Each of the plurality of second receiver modules is coupled to at least one of first receivers. Each of the plurality of second receiver modules includes a plurality of second receivers. Each of the second receivers reads the set of field information so as to determine whether the set of field information is designated thereto. Each of the plurality of LED driver groups is coupled to the at least one of the second receivers. Each of the plurality of LED driver groups includes a plurality of LED drivers.

Abstract: The apparatus for driving LED display includes a system control unit having a synchronization signal generator configured to generate a synchronization start signal and a plurality of phase locked loop circuits. Each of the phase locked loop circuits includes a divider coupled to the voltage controlled oscillator and configured to change the sequence of dividing ratios over a modulation period, a sigma delta modulator configured to generate a sequence of random numbers to the divider, and a spread spectrum modulation depth controller coupled to the sigma delta modulator and configured to receive the synchronization start signal from the synchronization signal generator. Upon receipt of the synchronization start signal, the spread spectrum modulation depth controller starts a spread spectrum modulation.

Abstract: An apparatus for driving LED display includes a plurality of phase locked loop circuits. Each of the phase locked loop circuits includes a divider configured to receive the voltage controlled output signal and generate the feedback signal, a memory configured to generate a modulation profile codes and a sigma delta block. The divider receives a randomized numbers so as to change a dividing ratio over a modulation period. The sigma delta block includes at least one sigma delta modulator and at least one gain block. The sigma delta block is configured to receive the modulation profile codes and generate the randomized numbers to the divider. Each of the at least one gain block is configured to generate a value that is multiplied to at least one of the at least one sigma delta modulator so as to change a spread spectrum modulation depth.

Abstract: The apparatus for driving LED display includes a system control unit having a synchronization signal generator configured to generate a synchronization start signal and a plurality of phase locked loop circuits. Each of the phase locked loop circuits includes a divider coupled to the voltage controlled oscillator and configured to change the sequence of dividing ratios over a modulation period, a sigma delta modulator configured to generate a sequence of random numbers to the divider, and a spread spectrum modulation depth controller coupled to the sigma delta modulator and configured to receive the synchronization start signal from the synchronization signal generator. Upon receipt of the synchronization start signal, the spread spectrum modulation depth controller starts a spread spectrum modulation.

Abstract: An apparatus for driving LED display includes a plurality of phase locked loop circuits. Each of the phase locked loop circuits includes a divider configured to receive the voltage controlled output signal and generate the feedback signal, a memory configured to generate a modulation profile codes and a sigma delta block. The divider receives a randomized numbers so as to change a dividing ratio over a modulation period. The sigma delta block includes at least one sigma delta modulator and at least one gain block. The sigma delta block is configured to receive the modulation profile codes and generate the randomized numbers to the divider. Each of the at least one gain block is configured to generate a value that is multiplied to at least one of the at least one sigma delta modulator so as to change a spread spectrum modulation depth.