Abstract: The present disclosure discloses a CO2 quantitative fluorescent sensing material, a preparation method and an application thereof. The preparation method for the CO2 quantitative fluorescent sensing material includes dissolving 9,10-diacrylic anthracene in a solvent to prepare 5-10 mg/mL of a first solution; dissolving MnCl2 or Mn(ClO4)2 in water to prepare 50-100 mg/mL of a second solution; mixing the first solution and the second solution; adding a diluted acid into the mixed solution; sealing and heating the mixed solution. This preparation method is simple. During application, an ionic liquid produced by a reaction of CO2 gas and an amine compound improves an aggregation-induced emission of the CO2 quantitative fluorescent sensing material and a fluorescence thereof is significantly improved. So that a fluorescent CO2 quantification is performed rapidly and accurately.

Abstract: The present disclosure discloses a CO2 quantitative fluorescent sensing material, a preparation method and an application thereof. The preparation method for the CO2 quantitative fluorescent sensing material includes dissolving 9,10-diacrylic anthracene in a solvent to prepare 5-10 mg/mL of a first solution; dissolving MnCl2 or Mn(ClO4)2 in water to prepare 50-100 mg/mL of a second solution; mixing the first solution and the second solution; adding a diluted acid into the mixed solution; sealing and heating the mixed solution. This preparation method is simple. During application, an ionic liquid produced by a reaction of CO2 gas and an amine compound improves an aggregation-induced emission of the CO2 quantitative fluorescent sensing material and a fluorescence thereof is significantly improved. So that a fluorescent CO2 quantification is performed rapidly and accurately.

Abstract: The present disclosure discloses a reversible continuous variable chromogenic material, a preparation method as well as an application thereof. The present disclosure relates to a field of chromogenic material. The reversible continuous variable chromogenic material crystallizes in a trigonal R3 space group. A fundamental asymmetric unit includes two 9,10-diacrylate anthracene ligands, two Mn2+ and ? ?-O. A plurality of fundamental asymmetric units connect with each other and form a three dimensional infinite network structure. This material is a chromogenic metal-organic framework which performs continuous variable fluorescence color in a wide color gamut. A preparation technology for this reversible continuous variable chromogenic material is facile.

Abstract: In some embodiments, a circuit comprises a plurality of memory banks, a column line tracking loop and/or a row line tracking loop, and a tracking circuit. The plurality of memory banks are arranged in a plurality of rows and a plurality of columns of memory building blocks. The column line tracking loop traverses at least a portion of the plurality of rows. The row line tracking loop traverses at least a portion of the plurality of columns. The tracking circuit is configured to receive a first edge of a first signal, cause the first edge of a first signal to be propagated through the column line tracking loop and/or through the row line tracking loop and cause a second edge of the first signal when receiving the propagated first edge of the first signal. The first signal is associated with accessing of the plurality of memory banks.

Abstract: In some embodiments, a circuit comprises a plurality of memory banks, a column line tracking loop and/or a row line tracking loop, and a tracking circuit. The plurality of memory banks are arranged in a plurality of rows and a plurality of columns of memory building blocks. The column line tracking loop traverses at least a portion of the plurality of rows. The row line tracking loop traverses at least a portion of the plurality of columns. The tracking circuit is configured to receive a first edge of a first signal, cause the first edge of a first signal to be propagated through the column line tracking loop and/or through the row line tracking loop and cause a second edge of the first signal when receiving the propagated first edge of the first signal. The first signal is associated with accessing of the plurality of memory banks.

Abstract: In some embodiments, a time division multiplexing (TDM) circuit is configured to receive an external clock signal and generate an internal clock signal that has at least one pulse during a clock cycle of the external clock signal. An address selector is configured to select a current address before a first time within one of the at least one pulse, and select a next address starting from the first time to generate a selected address. An address storage element is configured to receive the selected address from the address selector and provide a passed through or stored address. The provided address is the current address substantially throughout the one of the at least one pulse. A single-port (SP) memory is configured to access at least one SP memory cell at the address provided by the address storage element in response to the internal clock signal.

Abstract: Embodiments of the present invention relate to the field of communications, and provide a message transmitting method and device. The method includes: transmitting, by a user equipment UE, a radio resource control request to a base station, where the UE is in an enhanced uplink cell forward access channel CELL_FACH state and a system information block SIB5 includes an uplink interference value; when no radio resource control response message is received from the base station within a preset time and it is determined that the current number of times the radio resource control request is transmitted is smaller than a preset maximum number of transmissions, read an SIB7 periodically and obtain the uplink interference value; when determining, according to the uplink interference value, to transmit the radio resource control request message to the base station, transmit the radio resource control request message to the base station again.

Abstract: In some embodiments, a time division multiplexing (TDM) circuit is configured to receive an external clock signal and generate an internal clock signal that has at least one pulse during a clock cycle of the external clock signal. An address selector is configured to select a current address before a first time within one of the at least one pulse, and select a next address starting from the first time to generate a selected address. An address storage element is configured to receive the selected address from the address selector and provide a passed through or stored address. The provided address is the current address substantially throughout the one of the at least one pulse. A single-port (SP) memory is configured to access at least one SP memory cell at the address provided by the address storage element in response to the internal clock signal.

Abstract: A semiconductor chip comprises a word line configured to be driven by a word line driver. The semiconductor chip also comprises a plurality of bit lines. Each bit line of the plurality of bit lines is configured to transmit a signal to a respective bit line amplifier. The semiconductor device further comprises a plurality of memory cells. At least one memory cell of the plurality of memory cells is at an intersection of the word line and a bit line of the plurality of bit lines. The at least one memory cell of the plurality of memory cells is a type selected from at least two memory cell types based on a distance of the intersection from an end of the word line.

Abstract: A boost system for dual-port SRAM includes a comparator and a boost circuit. The comparator is configured to compare a first row address of a first port and a second row address of a second port, and output a first enable signal. The boost circuit is configured to boost a voltage difference between a first voltage source and a second voltage source according to the first enable signal.

Abstract: A boost system for dual-port SRAM includes a comparator and a boost circuit. The comparator is configured to compare a first row address of a first port and a second row address of a second port, and output a first enable signal. The boost circuit is configured to boost a voltage difference between a first voltage source and a second voltage source according to the first enable signal.

Abstract: A semiconductor chip comprises a word line configured to be driven by a word line driver. The semiconductor chip also comprises a plurality of bit lines. Each bit line of the plurality of bit lines is configured to transmit a signal to a respective bit line amplifier. The semiconductor device further comprises a plurality of memory cells. At least one memory cell of the plurality of memory cells is at an intersection of the word line and a bit line of the plurality of bit lines. The at least one memory cell of the plurality of memory cells is a type selected from at least two memory cell types based on a distance of the intersection from an end of the word line.

Abstract: Embodiments of the present invention relate to the field of communications, and provide a message transmitting method and device. The method includes: transmitting, by a user equipment UE, a radio resource control request to a base station, where the UE is in an enhanced uplink cell forward access channel CELL_FACH state and a system information block SIB5 includes an uplink interference value; when no radio resource control response message is received from the base station within a preset time and it is determined that the current number of times the radio resource control request is transmitted is smaller than a preset maximum number of transmissions, read an SIB7 periodically and obtain the uplink interference value; when determining, according to the uplink interference value, to transmit the radio resource control request message to the base station, transmit the radio resource control request message to the base station again.

Abstract: A semiconductor memory chip that has word lines driven by respective word line drivers and bit lines to carry signals to respective bit line amplifiers/drivers with memory cells at intersections of the word lines and bit lines memory cells. The semiconductor memory chip including various memory cell types, the type of memory cell at an intersection based on a position of the intersection among the word lines and bit lines.

Abstract: A semiconductor memory chip that has word lines driven by respective word line drivers and bit lines to carry signals to respective bit line amplifiers/drivers with memory cells at intersections of the word lines and bit lines memory cells. The semiconductor memory chip including various memory cell types, the type of memory cell at an intersection based on a position of the intersection among the word lines and bit lines.