Abstract: A method for analyzing circuit pattern is disclosed. The method includes the steps of: providing a plurality of monitor metal line structures formed on discrete locations of a substrate corresponding to different values of variable factors; performing a defect review to identify failure locations of the monitor metal line structures; determining a failure tendency of the monitor metal line structures so as to determine a boundary of the variable factors; and determining whether adjustment is to be made to product metal line structures.

Abstract: A method of manufacturing a semiconductor device is disclosed, which can completely remove hard mask residues left along boundaries between a high-voltage device region and STI structures after a dry etch process, by partially reducing a thickness of each of the exposed portion of the respective STI structures adjacent to the high-voltage device region so as to sufficiently expose the residues. As a result, after a portion of an Underlying pad oxide corresponding to the high-voltage device region is removed in a subsequent process, the exposed surface of the substrate is uniform with a smooth and clear border. Therefore, no sharp corners will emerge at a border of a gate oxide subsequently grown on the exposed surface of the substrate, and the gate oxide is thus morphologically improved, thereby resulting in an improvement of the reliability of the high-voltage semiconductor device being fabricated.

Abstract: A test pattern structure including a first conductive layer and a second conductive layer is provided. The second conductive layer is directly disposed on the first conductive layer and connected to the first conductive layer through a plurality of connection interfaces. The test pattern structure of the present invention can detect the interconnection failure quickly and correctly without SEM identification.

Abstract: A test pattern structure including a first conductive layer and a second conductive layer is provided. The second conductive layer is directly disposed on the first conductive layer and connected to the first conductive layer through a plurality of connection interfaces. The test pattern structure of the present invention can detect the interconnection failure quickly and correctly without SEM identification.