Abstract: A method for testing terminals includes determining a quantity of terminals to be tested; testing each terminal to be tested in a testing environment and obtaining a quantity of testing results; each testing result includes an actual transmitting power and/or a receiving signal strength; obtaining a first fitting function based on the actual transmitting power, and/or obtaining a second fitting function based on the receiving signal strength; and controlling a target terminal to transmit signals, calculating an actual transmitting power of the target terminal by the first fitting function, and/or controlling the target terminal to receive signals, calculating a receiving signal strength of the target terminal by the second fitting function. A computer apparatus and a non-transitory computer readable medium for testing terminals are also disclosed.

Abstract: A method for testing terminals includes determining a quantity of terminals to be tested; testing each terminal to be tested in a testing environment and obtaining a quantity of testing results; each testing result includes an actual transmitting power and/or a receiving signal strength; obtaining a first fitting function based on the actual transmitting power, and/or obtaining a second fitting function based on the receiving signal strength; and controlling a target terminal to transmit signals, calculating an actual transmitting power of the target terminal by the first fitting function, and/or controlling the target terminal to receive signals, calculating a receiving signal strength of the target terminal by the second fitting function. A computer apparatus and a non-transitory computer readable medium for testing terminals are also disclosed.

Abstract: A high-linearity CMOS input buffer circuit is provided for neutralizing non-linearity of follower circuits' transconductance and output impedance resulting from input signals' variation. In doing so, the linearity of CMOS input buffer is improved. The buffer circuit includes a CMOS input follower circuit, a linearity improvement circuit of follower transistor, a current source load, and a linearity improvement circuit of load impedance. The buffer circuit is fabricated in standard CMOS process, featuring low cost, simplicity and strong linearity at high frequency. It has wide applications in analog and hybrid analog-digital CMOS ICs requiring high linearity input buffer.

Abstract: A high-linearity CMOS input buffer circuit is provided for neutralizing non-linearity of follower circuits' transconductance and output impedance resulting from input signals' variation. In doing so, the linearity of CMOS input buffer is improved. The buffer circuit includes a CMOS input follower circuit, a linearity improvement circuit of follower transistor, a current source load, and a linearity improvement circuit of load impedance. The buffer circuit is fabricated in standard CMOS process, featuring low cost, simplicity and strong linearity at high frequency. It has wide applications in analog and hybrid analog-digital CMOS ICs requiring high linearity input buffer.