Abstract: An example system includes: interface circuitry; programmable circuitry; and instructions to cause the programmable circuitry to: reserve first memory addresses of a host system, the first memory addresses reserved for emulation of a guest system, the guest system based on a first instruction set architecture that is different from a second instruction set architecture of the host system; reserve second memory addresses of the host system that are contiguous with the first memory addresses, the second memory addresses reserved for a first emulated memory access instruction associated with an overflow in the guest system; reserve third memory addresses of the host system for a second emulated memory access instruction associated with an underflow in the guest system; and set memory access privileges of the second and third memory addresses to prevent at least one of a read, a write, or an execution access for the second and third memory addresses.

Abstract: One embodiment provides a device. The device includes a processor; a memory; and translator logic. The processor is to execute a host instruction set. The translator logic is to determine whether an offset is a constant and whether the offset is greater than zero and less than a maximum offset in response to receiving a guest memory access instruction that contains a base address plus or minus the offset, the maximum offset related to at least one of a host instruction set architecture (ISA) and a guest ISA.

Abstract: Various embodiments include nested emulation for a source application and source emulator. Duplicate source ISA libraries redirect the source emulator library calls to a target library, thereby forcing the native emulator through proper emulation channels between first and second ISAs. Other embodiments concern accelerating dynamic linking by determining certain function calls that, rather than being processed through emulation of PLT code, are instead directly called without the need for PLT code translation. Some embodiments address both nested emulation and accelerated dynamic linking but other embodiments include one of nested emulation and accelerated dynamic linking. Other embodiments are described herein.

Abstract: Various embodiments include nested emulation for a source application and source emulator. Duplicate source ISA libraries redirect the source emulator library calls to a target library, thereby forcing the native emulator through proper emulation channels between first and second ISAs. Other embodiments concern accelerating dynamic linking by determining certain function calls that, rather than being processed through emulation of PLT code, are instead directly called without the need for PLT code translation. Some embodiments address both nested emulation and accelerated dynamic linking but other embodiments include one of nested emulation and accelerated dynamic linking. Other embodiments are described herein.

Abstract: Systems and methods are provided in example embodiments for performing binary translation. A binary translation system converts, by a translator module, source instructions to target instructions. The binary translation system identifies a condition code block in the source instructions, where the condition code block includes a plurality of condition bits. In response to identifying the condition code block, the binary translation system provides an optimizer module to convert the condition code block. Then, the binary translation system performs a pre-execution on the condition code block to resolve the plurality of condition bits in the condition code block.

Abstract: Methods, apparatuses and storage medium associated with execution of application code having multiple ISAs, are disclosed. In various embodiments, a runtime environment may execute application code having multiple instruction set architectures. The runtime environment may be configured to execute first code of the application code according to a first instruction set architecture, while also configured to execute second code of the application code according to a second instruction set architecture that extends the first instruction set architecture. Using gates, the runtime environment may be adapted to adapt an interaction from the first code to the second instruction set architecture and/or adapt an interaction from the second code to the first instruction set architecture and, subsequently, return to executing the application code according to the first instruction set architecture or the second instruction set architecture, respectively. Other embodiments may be disclosed or claimed.

Abstract: One embodiment provides a device. The device includes a processor; a memory; and translator logic. The processor is to execute a host instruction set. The translator logic is to determine whether an offset is a constant and whether the offset is greater than zero and less than a maximum offset in response to receiving a guest memory access instruction that contains a base address plus or minus the offset, the maximum offset related to at least one of a host instruction set architecture (ISA) and a guest ISA.

Abstract: Various embodiments include nested emulation for a source application and source emulator. Duplicate source ISA libraries redirect the source emulator library calls to a target library, thereby forcing the native emulator through proper emulation channels between first and second ISAs. Other embodiments concern accelerating dynamic linking by determining certain function calls that, rather than being processed through emulation of PLT code, are instead directly called without the need for PLT code translation. Some embodiments address both nested emulation and accelerated dynamic linking but other embodiments include one of nested emulation and accelerated dynamic linking. Other embodiments are described herein.

Abstract: Systems and methods may provide translation cache closure and consistent data recovery in dynamic code generating system. An apparatus may group translation cache together and restore a translation cache snapshot as a whole. Chaining between translations may be maintained during saving and restoration.

Abstract: Apparatuses, methods and storage media associated with multiple processor modes execution are described herein. In embodiments, an apparatus may include a processor with a plurality of processor modes, including a first processor mode to address a first address space, and a second processor mode to address a second address space, the second address space including the first address space. The apparatus may further include a signal handler to handle a signal from a kernel, in the first processor mode; and a signal handler wrapper to switch the processor to the second processor mode on delivery of the signal from the kernel, save a current extra context of the second processor mode from the second register file to a user stack, switch the processor back to the first processor mode, then invoke the signal handler to handle the signal. Other embodiments may be described or claimed.

Abstract: Methods, apparatuses and storage medium associated with execution of application code having multiple ISAs, are disclosed. In various embodiments, a runtime environment may execute application code having multiple instruction set architectures. The runtime environment may be configured to execute first code of the application code according to a first instruction set architecture, while also configured to execute second code of the application code according to a second instruction set architecture that extends the first instruction set architecture. Using gates, the runtime environment may be adapted to adapt an interaction from the first code to the second instruction set architecture and/or adapt an interaction from the second code to the first instruction set architecture and, subsequently, return to executing the application code according to the first instruction set architecture or the second instruction set architecture, respectively. Other embodiments may be disclosed or claimed.

Abstract: Apparatuses, methods and storage media associated with multiple processor modes execution are described herein. In embodiments, an apparatus may include a processor with a plurality of processor modes, including a first processor mode to address a first address space, and a second processor mode to address a second address space, the second address space including the first address space. The apparatus may further include a signal handler to handle a signal from a kernel, in the first processor mode; and a signal handler wrapper to switch the processor to the second processor mode on delivery of the signal from the kernel, save a current extra context of the second processor mode from the second register file to a user stack, switch the processor back to the first processor mode, then invoke the signal handler to handle the signal. Other embodiments may be described or claimed.

Abstract: Systems and methods may provide translation cache closure and consistent data recovery in dynamic code generating system. An apparatus may group translation cache together and restore a translation cache snapshot as a whole. Chaining between translations may be maintained during saving and restoration.

Abstract: Systems and methods are provided in example embodiments for performing binary translation. A binary translation system converts, by a translator module, source instructions to target instructions. The binary translation system identifies a condition code block in the source instructions, where the condition code block includes a plurality of condition bits. In response to identifying the condition code block, the binary translation system provides an optimizer module to convert the condition code block. Then, the binary translation system performs a pre-execution on the condition code block to resolve the plurality of condition bits in the condition code block.

Abstract: Various embodiments include nested emulation for a source application and source emulator. Duplicate source ISA libraries redirect the source emulator library calls to a target library, thereby forcing the native emulator through proper emulation channels between first and second ISAs. Other embodiments concern accelerating dynamic linking by determining certain function calls that, rather than being processed through emulation of PLT code, are instead directly called without the need for PLT code translation. Some embodiments address both nested emulation and accelerated dynamic linking but other embodiments include one of nested emulation and accelerated dynamic linking. Other embodiments are described herein.