Patents by Inventor Xueren Zhang
Xueren Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10658238Abstract: Embodiments are directed to a package that includes an electric device having a recess. In one embodiment, the electric device is a sensor and the recess reduces signal drift of the sensor caused by thermal expansion of the package. In another embodiment, the recess is substantially filled with adhesive material, thus increasing adhesion between the electric device and a substrate of the package while at the same time allowing for lower adhesive fillets.Type: GrantFiled: October 16, 2017Date of Patent: May 19, 2020Assignee: STMICROELECTRONICS PTE LTDInventors: Kim-Yong Goh, Xueren Zhang, Yiyi Ma
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Publication number: 20180040514Abstract: Embodiments are directed to a package that includes an electric device having a recess. In one embodiment, the electric device is a sensor and the recess reduces signal drift of the sensor caused by thermal expansion of the package. In another embodiment, the recess is substantially filled with adhesive material, thus increasing adhesion between the electric device and a substrate of the package while at the same time allowing for lower adhesive fillets.Type: ApplicationFiled: October 16, 2017Publication date: February 8, 2018Inventors: Kim-Yong Goh, Xueren Zhang, Yiyi Ma
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Patent number: 9824924Abstract: Embodiments are directed to a package that includes an electric device having a recess. In one embodiment, the electric device is a sensor and the recess reduces signal drift of the sensor caused by thermal expansion of the package. In another embodiment, the recess is substantially filled with adhesive material, thus increasing adhesion between the electric device and a substrate of the package while at the same time allowing for lower adhesive fillets.Type: GrantFiled: March 29, 2013Date of Patent: November 21, 2017Assignee: STMicroelectronics Pte Ltd.Inventors: Kim-Yong Goh, Xueren Zhang, Yiyi Ma
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Patent number: 9679870Abstract: An integrated circuit (IC) device includes an IC and encapsulating material surrounding the IC. Leads are coupled to the IC and extend outwardly from sides of the encapsulating material, with each lead having three contiguous exposed segments with upper and lower bends defining a Z-shape. In another example, the leads include an upper horizontal segment, lower horizontal segment, and intermediate curved segment extending upwardly from the upper horizontal segment and downwardly to the lower horizontal segment.Type: GrantFiled: December 10, 2014Date of Patent: June 13, 2017Assignee: STMicroelectronics Pte LtdInventors: Yiyi Ma, Kim-Yong Goh, Xueren Zhang, Wei Zhen Goh
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Patent number: 9620438Abstract: An electronic device includes an integrated circuit chip mounted to a heat slug. The heat slug has a peripheral region having first thickness along a first direction, the peripheral region surrounding a recess region (having a second, smaller, thickness along the first direction) that defines a chip mounting surface along a second direction perpendicular to the first direction. The recess region defines side borders and a nook extends into the heat slug along the side borders. An insulating body embeds the integrated circuit one chip and heat slug. Material of the insulating body fills the nook.Type: GrantFiled: February 6, 2015Date of Patent: April 11, 2017Assignees: STMICROELECTRONICS (MALTA) LTD, STMICROELECTRONICS S.R.L., STMICROELECTRONICS PTE LTDInventors: Roseanne Duca, Valter Motta, Xueren Zhang, Kim-Yong Goh
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Patent number: 9576912Abstract: A wafer level chip scale package (WLCSP) includes a semiconductor substrate, a back end of line (BEOL) layer on the semiconductor substrate and having a peripheral edge recessed inwardly from an adjacent peripheral edge of the semiconductor substrate. A first dielectric layer is over the BEOL layer and wraps around the peripheral edge of the BEOL layer. A redistribution layer is over the first dielectric layer and a second dielectric layer is over the redistribution layer.Type: GrantFiled: December 3, 2015Date of Patent: February 21, 2017Assignee: STMICROELECTRONICS PTE LTDInventors: Yiyi Ma, Kim-Yong Goh, Xueren Zhang
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Publication number: 20160293512Abstract: An electronic device may include a substrate, an active IC die above the substrate, and a dummy IC die above the active IC die. The electronic device may include a first adhesive layer between the active IC die and the dummy IC die, and a heat sink layer above the dummy IC die and extending laterally outwardly to define a gap between the substrate and opposing portions of the heat sink layer.Type: ApplicationFiled: March 31, 2015Publication date: October 6, 2016Inventors: Yiyi MA, Kim-Yong GOH, Xueren ZHANG
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Patent number: 9449912Abstract: An integrated circuit (IC) module for an IC card includes a plurality of IC card contacts in side-by-side relation. A dielectric support layer is above the contact layer and has a plurality of openings and a first coefficient of thermal expansion (CTE). An IC die is above the dielectric support layer and includes a plurality of bond pads. A bond wire extends from a respective bond pad to a corresponding contact through an adjacent opening in the dielectric support layer. A respective body of fill material is within each opening and has a second CTE. A mold compound body is above the dielectric support layer, the bodies of fill material, and surrounding the IC die. The mold compound body has a third CTE. The first CTE is closer to the second CTE than to the third CTE.Type: GrantFiled: June 11, 2015Date of Patent: September 20, 2016Assignees: STMICROELECTRONICS PTE LTD, STMICROELECTRONICS (MALTA) LTDInventors: Xueren Zhang, Kim-Yong Goh, Roseanne Duca
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Publication number: 20160190029Abstract: A method of making an electronic device may include positioning an integrated circuit (IC) die on an upper surface of a grid array substrate having connections on a lower surface thereof and coupling respective bond pads of the IC die to the grid array with bond wires. The method may also include forming a first encapsulating layer over the IC die and bond wires and positioning a heat spreader on the substrate above the first encapsulating layer after forming the first encapsulating layer. The method may further include forming a second encapsulating layer over the first encapsulating layer and embedding the heat spreader in the second encapsulating layer.Type: ApplicationFiled: December 30, 2014Publication date: June 30, 2016Inventors: Kim-Yong GOH, Yiyi Ma, Xueren Zhang
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Patent number: 9379034Abstract: A method of making an electronic device may include positioning an integrated circuit (IC) die on an upper surface of a grid array substrate having connections on a lower surface thereof and coupling respective bond pads of the IC die to the grid array with bond wires. The method may also include forming a first encapsulating layer over the IC die and bond wires and positioning a heat spreader on the substrate above the first encapsulating layer after forming the first encapsulating layer. The method may further include forming a second encapsulating layer over the first encapsulating layer and embedding the heat spreader in the second encapsulating layer.Type: GrantFiled: December 30, 2014Date of Patent: June 28, 2016Assignee: STMICROELECTRONICS PTE LTDInventors: Kim-Yong Goh, Yiyi Ma, Xueren Zhang
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Publication number: 20160172262Abstract: An integrated circuit (IC) device includes an IC and encapsulating material surrounding the IC. Leads are coupled to the IC and extend outwardly from sides of the encapsulating material, with each lead having three contiguous exposed segments with upper and lower bends defining a Z-shape. In another example, the leads include an upper horizontal segment, lower horizontal segment, and intermediate curved segment extending upwardly from the upper horizontal segment and downwardly to the lower horizontal segment.Type: ApplicationFiled: December 10, 2014Publication date: June 16, 2016Inventors: Yiyi MA, Kim-Yong GOH, Xueren ZHANG, Wei Zhen GOH
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Patent number: 9257372Abstract: A surface mount package of a semiconductor device, has: an encapsulation, housing at least one die including semiconductor material; and electrical contact leads, protruding from the encapsulation to be electrically coupled to contact pads of a circuit board; the encapsulation has a main face designed to face a top surface of the circuit board, which is provided with coupling features designed for mechanical coupling to the circuit board to increase a resonant frequency of the mounted package. The coupling features envisage at least a first coupling recess defined within the encapsulation starting from the main face, designed to be engaged by a corresponding coupling element fixed to the circuit board, thereby restricting movements of the mounted package.Type: GrantFiled: September 19, 2013Date of Patent: February 9, 2016Assignees: STMicroelectronics (Mala) Ltd, STMicroelectronics Pte LtdInventors: Roseanne Duca, Kim-Yong Goh, Xueren Zhang, Kevin Formosa
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Publication number: 20150235929Abstract: An electronic device includes an integrated circuit chip mounted to a heat slug. The heat slug has a peripheral region having first thickness along a first direction, the peripheral region surrounding a recess region (having a second, smaller, thickness along the first direction) that defines a chip mounting surface along a second direction perpendicular to the first direction. The recess region defines side borders and a nook extends into the heat slug along the side borders. An insulating body embeds the integrated circuit one chip and heat slug. Material of the insulating body fills the nook.Type: ApplicationFiled: February 6, 2015Publication date: August 20, 2015Applicants: STMICROELECTRONICS (MALTA) LTD, STMICROELECTRONICS S.R.L., STMICROELECTRONICS PTE LTDInventors: Roseanne Duca, Valter Motta, Xueren Zhang, Kim-Yong Goh
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Publication number: 20150084171Abstract: A non-lead (QFN) semiconductor package is disclosed. The package includes a die attach pad and a semiconductor die supported by the die attached pad. The semiconductor die includes a plurality of pads on an active surface thereof. The package further includes a plurality of terminal leads, an encapsulant that encapsulates the semiconductor die, and a redistribution layer including a plurality of interconnections electrically connecting the pads to the terminal leads. A method of making the package is also disclosed.Type: ApplicationFiled: September 23, 2013Publication date: March 26, 2015Applicant: STMicroelectronics Pte. Ltd.Inventors: Yiyi Ma, Kim-Yong Goh, Xueren Zhang
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Publication number: 20140291812Abstract: Embodiments are directed to a package that includes an electric device having a recess. In one embodiment, the electric device is a sensor and the recess reduces signal drift of the sensor caused by thermal expansion of the package. In another embodiment, the recess is substantially filled with adhesive material, thus increasing adhesion between the electric device and a substrate of the package while at the same time allowing for lower adhesive fillets.Type: ApplicationFiled: March 29, 2013Publication date: October 2, 2014Applicant: STMicroelectronics Pte Ltd.Inventors: Kim-Yong Goh, Xueren Zhang, Yiyi Ma
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Patent number: 8800391Abstract: A force sensor to measure a force from a load includes a plunger, a flexible disc-shaped membrane, a support plate and a silicon die. The plunger is configured to receive the force from the load, and has a ring-shaped groove at the lower surface. The membrane has a ring-shaped upper bump at the upper surface configured to complementarily fit into the groove at the lower surface of plunger and a ring-shaped lower bump at lower upper surface. The support plate has a ring-shaped groove for complementary fit into the lower bump on the lower surface of the membrane. The silicon die is centrally mounted on the membrane and comprises piezo-resistors with resistance that varies when deformed by the force. Force received by the plunger is transmitted to the membrane, causing the membrane to flex and bending or compressing of the silicon die, resulting in the measurement of the force.Type: GrantFiled: May 11, 2007Date of Patent: August 12, 2014Assignee: STMicroelectronics Asia Pacific Pte, Ltd.Inventors: Xueren Zhang, Andrea Lorenzo Vitali, Federico Giovanni Ziglioli, Bruno Biffi, Tong Yan Tee
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Patent number: 8796826Abstract: A device and method for minimizing the forces that may compromise a lead frame mount to a support structure in an integrated circuit die package during various packaging method steps. When a window clamp is used to provide pressure during a lead frame bonding step or during a wire bonding step during packaging, the vertical force applied by the window clamp may be transferred in lateral direction by the physical contour of the top plate of the support structure. By changing the physical contour of the top plate of the support structure, such as by disposing a specific kind of contoured protrusion, one may minimize or eliminate the lateral forces that act against achieving a solid bond of the lead frame to the support structure. Further, during wire bonding, the same minimization or elimination of lateral forces lead to improved wire bonding.Type: GrantFiled: December 22, 2011Date of Patent: August 5, 2014Assignee: STMicroelectronics Pte LtdInventors: Xueren Zhang, Kim-Yong Goh, Wingshenq Wong
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Patent number: 8772943Abstract: An integrated circuit die has a dielectric layer positioned over all the contact pads on the integrated circuit die. Openings are provided in the dielectric layer over each of the contact pads of the integrated circuit die in order to permit electrical coupling to be made between the integrated circuit and circuit boards outside of the die. For those contact pads located in the central region of the die, the opening in the dielectric layer is in a central region of the contact pad. For those contact pads located in a peripheral region of the die, spaced adjacent the perimeter die, the opening in the dielectric layer is offset from the center of the contact pad and is positioned closer to the central region of the die than the center of the contact pad is to the central region of the die.Type: GrantFiled: December 7, 2011Date of Patent: July 8, 2014Assignee: STMicroelectronics Pte Ltd.Inventors: Xueren Zhang, Kim-Yong Goh
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Publication number: 20140091443Abstract: A surface mount package of a semiconductor device, has: an encapsulation, housing at least one die including semiconductor material; and electrical contact leads, protruding from the encapsulation to be electrically coupled to contact pads of a circuit board; the encapsulation has a main face designed to face a top surface of the circuit board, which is provided with coupling features designed for mechanical coupling to the circuit board to increase a resonant frequency of the mounted package. The coupling features envisage at least a first coupling recess defined within the encapsulation starting from the main face, designed to be engaged by a corresponding coupling element fixed to the circuit board, thereby restricting movements of the mounted package.Type: ApplicationFiled: September 19, 2013Publication date: April 3, 2014Applicants: STMicroelectronics Pte Ltd, STMicroelectronics (Malta) LtdInventors: Roseanne Duca, Kim-Yong Goh, Xueren Zhang, Kevin Formosa
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Patent number: 8592980Abstract: An interconnect structure for use in an integrated circuit is provided. The interconnect structure includes a first low-K dielectric material. The first low-K material may be modified with a first group of carbon nanotubes (CNTs) and disposed on a metal line. The first low-K material is modified by dispersing the first group of CNTs in a solution, spinning the solution onto a silicon wafer and curing the solution to form the first low-K material modified with the first CNTs. The metal line includes a top layer and a bottom layer connected by a metal via. The interconnect structure also includes a second low-K dielectric material modified with a second group of CNTs and disposed on the bottom layer. Accordingly, embodiments the present disclosure could help to increase the mechanical strength of the low-K material or the entire interconnect structure.Type: GrantFiled: March 7, 2007Date of Patent: November 26, 2013Assignee: STMicroelectronics Asia Pacific Pte., Ltd.Inventors: Shanzhong Wang, Valeriy Nosik, Tong Yan Tee, Xueren Zhang