Patents by Inventor Xueshi Yang

Xueshi Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Selectively scheduling memory accesses in parallel based on access speeds of memory
    Patent number: 8762654
    Abstract: Devices, systems, methods, and other embodiments associated with selectively scheduling memory accesses in parallel are described. In one embodiment, a method determines an access speed for a page request. The access speed is a number of clock cycles used to access a memory device of a group of memory devices. The page request is a request to access a memory page mapped to the memory device. Different page requests are selectively scheduled to access different memory devices in parallel. The different page requests access the different memory devices in a same number of clock cycles.
    Type: Grant
    Filed: June 15, 2009
    Date of Patent: June 24, 2014
    Assignee: Marvell International Ltd.
    Inventors: Xueshi Yang, Chi Kong Lee
  • System with servo clock and write clock based phase estimation for discontinuous media writing
    Patent number: 8755139
    Abstract: A system including a storage device, a channel module, a sampling module, a first phase module, and an adjustment module. The storage device includes servo sectors, and discontinuous media with bit islands. The channel module reads the servo sectors based on a servo clock to generate an analog signal. The sampling module samples the analog signal based on a servo clock signal to generate first samples, and based on a write clock signal to generate second samples. The first phase module estimates a phase of the write clock signal based on the first samples, and the second samples. The adjustment module adjusts the phase of the write clock signal based on the estimated phase of the write clock signal. The channel module, based on the write clock signal with the adjusted phase, writes data to the bit islands of the discontinuous media.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: June 17, 2014
    Assignee: Marvell International Ltd.
    Inventors: Qiyue Zou, Xueshi Yang, Gregory Burd
  • SYSTEMS AND METHODS FOR GENERATING SOFT INFORMATION IN NAND FLASH
    Publication number: 20140160855
    Abstract: Systems and methods are provided to generate soft information related to the threshold voltage of a memory cell. A range of threshold voltages for the memory cell is divided into subregions of threshold voltage values herein referred to as bins. An output of the memory cell in response to an applied reference signal is measured. The applied reference signal includes a voltage value and position information. A single bin is identified based on the position information of the reference signal. The identified bin is split into more than one bin based on the output of the memory cell and the voltage value of the reference signal. The newly split bins and all the other bins that were not split are assigned new bin indices.
    Type: Application
    Filed: February 11, 2014
    Publication date: June 12, 2014
    Applicant: MARVELL WORLD TRADE LTD.
    Inventors: Zhengang Chen, Gregory Burd, Shashi Kiran Chilappagari, Xueshi Yang
  • PROGRAMMING NONVOLATILE MEMORY BASED ON STATISTICAL ANALYSIS OF CHARGE LEVEL DISTRIBUTIONS OF MEMORY CELLS
    Publication number: 20140157068
    Abstract: A system includes a read module, a statistical data generating module, and a storing module. The read module reads charge levels of nonvolatile memory cells and generates read signals. The statistical data generating module generates statistical data based on the read signals. The storing module stores the statistical data. The read module generates the read signals based on the charge levels of the nonvolatile memory cells and the statistical data.
    Type: Application
    Filed: February 4, 2014
    Publication date: June 5, 2014
    Applicant: Marvell World Trade LTD.
    Inventors: Zining Wu, Xueshi Yang
  • Write pre-compensation for nonvolatile memory
    Patent number: 8743616
    Abstract: A system including an interference module and a programming module. The interference module is configured to generate interference values based on (i) a state to which a memory cell is to be programmed and (ii) states of one or more memory cells located near the memory cell, and store the interference values. The interference values indicate effects of the states of the one or more memory cells on the state to which the memory cell is to be programmed. The programming module is configured to determine a programming value to program the memory cell to the state based on one or more of the interference values.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: June 3, 2014
    Assignee: Marvell International Ltd.
    Inventors: Zining Wu, Xueshi Yang, Pantas Sutardja
  • Method and system for ceasing access to memory cells of flash memory when less than a maximum number of correctable errors for an error correction code exists
    Patent number: 8738996
    Abstract: A system includes a flash memory, an encoder, a first interface, a decoder and a controller. The encoder is configured to (i) receive data, and (ii) encode the data based on an error correction code. The first interface is configured to (i) write the encoded data to a memory cells in the flash memory, and (ii) read the encoded data back from the memory cells. The decoder is configured to (i) decode the encoded data read back from the memory cells, and (ii) based on the decoded data, determine a number of decoding errors for the plurality of memory cells. The controller is configured to, in response to the number of decoding errors being greater than or equal to a first threshold, cease accessing the memory cells. The first threshold is less than a maximum number of errors correctable by the error correction code for the memory cells.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: May 27, 2014
    Assignee: Marvell International Ltd.
    Inventors: Chen Kuo Huang, Sui-Hung Fred Au, Xueshi Yang, Lau Nguyen
  • Method and apparatus for decoding a data sector including user data and non-user data
    Patent number: 8739003
    Abstract: The disclosure provides a method that includes receiving a data sector of a plurality of data tiles, wherein each of the plurality of data tiles includes either nuisance data or user data, decoding the received data sector, using an error correction code, to generate a decoded data sector, and determining an error in the decoded data sector. The method further includes identifying, in response to determining the error, at least one data tile from a first plurality of data tiles, such that each of the identified at least one data tiles potentially includes nuisance data, and generating a modified data sector from the received data sector, by correcting at least one of the at least one data tiles in the received data sector.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 27, 2014
    Assignee: Marvell International Ltd.
    Inventors: Xueshi Yang, Gregory Burd
  • Pilot placement for non-volatile memory
    Patent number: 8732432
    Abstract: A system including a write module, a read module, and a signal processing module. The write module is configured to write pilot data, having a first predetermined pattern, in a page of memory cells. The pilot data are interspersed with user data stored in the page. The read module is configured to read the pilot data and to generate pilot signals based on reading the pilot data. The signal processing module is configured to compare the pilot signals and the pilot data, and to estimate, based on a comparison of the pilot signals and the pilot data, a disturbance to the user data.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: May 20, 2014
    Assignee: Marvell World Trade, LTD.
    Inventors: Xueshi Yang, Zining Wu, Pantas Sutardja
  • Tensor product codes for flash
    Patent number: 8732543
    Abstract: In embodiments, data may be encoded based on a tensor product code by encoding incoming data to produce first codewords, and encoding the first codewords to produce second codewords. The incoming data may be combined with the second codewords to produce messages, which can then be transmitted and/or stored. Decoding a received message may include encoding a data portion to produce an intermediate code, and decoding the intermediate code using a codeword portion of the message to produce a corrected codeword. The data portion may then be decoded using the corrected codeword to recover data from the message.
    Type: Grant
    Filed: July 18, 2011
    Date of Patent: May 20, 2014
    Assignee: Marvell International Ltd.
    Inventor: Xueshi Yang
  • Adaptive read and write systems and methods for memory cells
    Patent number: 8725929
    Abstract: Adaptive memory read and write systems and methods are provided that may compute estimated means and variances of multi-level memory cells to facilitate writing and reading of data to and from the multi-level memory cells are described herein. The systems may include an apparatus comprising multi-level memory cells, and an estimation block configured to compute estimated means and variances of level distributions of the multi-level memory cells by processing signal samples provided by at least a subset of the multi-level memory cells, the estimated means and variances to be used to facilitate writing and/or reading of data to and/or from at least selected ones of the multi-level memory cells, the multi-level memory cells having M-levels where M is an integer greater than 1, and each of the level distributions is associated with a corresponding level of the M-levels.
    Type: Grant
    Filed: January 7, 2009
    Date of Patent: May 13, 2014
    Assignee: Marvell World Trade Ltd.
    Inventors: Xueshi Yang, Zining Wu, Gregory Burd
  • UPDATING REFERENCE VOLTAGES TO COMPENSATE FOR CHANGES IN THRESHOLD VOLTAGE DISTRIBUTIONS OF NONVOLATILE MEMORY CELLS
    Publication number: 20140126294
    Abstract: A system including a reference voltage module configured to generate one or more reference voltages for determining states of a plurality of memory cells of a nonvolatile memory, where the plurality of memory cells have a threshold voltage distribution. A divider module divides, in response to a change in the threshold voltage distribution, a voltage range into a plurality of regions. An update module updates, to compensate for the change in the threshold voltage distribution, one of the reference voltages to a voltage value associated with one of the plurality of regions.
    Type: Application
    Filed: January 14, 2014
    Publication date: May 8, 2014
    Applicant: Marvell World Trade LTD.
    Inventor: Xueshi Yang
  • Selectively accessing faster or slower multi-level cell memory
    Patent number: 8706951
    Abstract: Devices, systems, methods, and other embodiments associated with selectively accessing memory are described. In one embodiment, a method detects an indication indicative of whether to program fast access pages or slow access pages of a flash memory. In response to the detected indication, data is programmed from a volatile memory: (1) to the fast access pages of the flash memory while skipping the slow access pages, or (2) to the slow access pages while skipping the fast access pages.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: April 22, 2014
    Assignee: Marvell World Trade Ltd.
    Inventors: Xueshi Yang, Tony Yoon
  • Sequence detection for flash memory with inter-cell interference
    Patent number: 8705285
    Abstract: A system including a read module and a sequence detector module. The read module is configured to read a plurality of memory cells located along a bit line or a word line of a memory array and to generate a plurality of read signals. The sequence detector module is configured to detect a sequence of data stored in the plurality of memory cells based on (i) the plurality of read signals and (ii) a plurality of reference signals associated with the plurality of memory cells. One of the plurality of reference signals associated with a first memory cell of the plurality of memory cells includes (i) a first signal and (ii) a second signal. The first signal is free of interference from a second memory cell adjacent to the first memory cell along the bit line or the word line. The second signal includes interference from the second memory cell.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: April 22, 2014
    Assignee: Marvell World Trade Ltd.
    Inventors: Xueshi Yang, Zining Wu
  • Systems and methods for improving error distributions in multi-level cell memory systems
    Patent number: 8699269
    Abstract: A state set module arranges states of a memory cell in a first and a second sequence in a first and a second state set, respectively. The memory cell stores first and second bits when programmed to a state. When the states in the first and second state sets are accessed respectively in the first and the second sequence, the first and second bits of the states in the first and second state sets exhibit different number of logical transitions. A write module receives first and second sets of bits to be written as the first and second bits in a plurality of memory cells, and selects states from the first and second state sets in an alternating pattern to write the first and second sets of bits as the first and second bits in the plurality of memory cells.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: April 15, 2014
    Assignee: Marvell International Ltd.
    Inventor: Xueshi Yang
  • Method and apparatus for calibrating a read/write channel in a memory arrangement
    Patent number: 8693275
    Abstract: A memory arrangement including a memory block and a controller. The memory block comprises a plurality of memory cells, wherein each memory cell operable to store one of a plurality of different levels of charge. The controller is configured to write (i) a first reference signal threshold into a first memory cell and (ii) a second reference signal threshold into a second memory cell. The first reference signal threshold corresponds to a first level of charge of the plurality of different levels of charge, and the second reference signal threshold corresponds to a second level of charge of the plurality of different levels of charge. Each of the first level of charge and the second level of charge is used to calibrate a read back of any of the one of the plurality of different levels of charge stored among the plurality of memory cells in the memory block.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: April 8, 2014
    Assignee: Marvell International Ltd.
    Inventors: Aditya Ramamoorthy, Gregory Burd, Xueshi Yang
  • Systems and methods for performing multi-state bit flipping in an LDPC decoder
    Patent number: 8694868
    Abstract: Systems and methods are provided for decoding data using hard decisions and soft information. In particular, the systems and methods described herein are directed to decoders having variable nodes and check nodes, each with multiple states. The systems and methods include receiving, at a decoder during a first iteration, values for each of a plurality of variable nodes, and determining, during a second iteration, one or more indications for each of a plurality of check nodes based on the one or more values of the variable nodes received during the first iteration. The methods further include updating, at the decoder during the second iteration, the values for each of the variable nodes based on the values of the respective variable node received during the first iteration, and the indications for each of the plurality connected check nodes during the first iteration.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: April 8, 2014
    Assignee: Marvell International Ltd.
    Inventors: Shashi Kiran Chilappagari, Nedeljko Varnica, Xueshi Yang, Gregory Burd
  • Sensor-aided patterned magnetic media synchronization systems
    Patent number: 8687304
    Abstract: A write clock synchronization system includes a first module configured to generate a write clock signal. A second module is configured to, based on a sensor signal received, detect a pattern of bit islands on bit-patterned media. The second module is configured to determine a phase error of the write clock signal based on the pattern of the bit islands. A third module is configured to at least one of adjust or select a phase of the write clock signal based on the phase error.
    Type: Grant
    Filed: January 17, 2011
    Date of Patent: April 1, 2014
    Assignee: Marvell International, Ltd.
    Inventors: Qiyue Zou, Xueshi Yang, Gregory Burd
  • Systems and methods for generating soft information in NAND flash
    Patent number: 8681564
    Abstract: Systems and methods are provided to generate soft information related to the threshold voltage of a memory cell. A range of threshold voltages for the memory cell is divided into subregions of threshold voltage values herein referred to as bins. An output of the memory cell in response to an applied reference signal is measured. The applied reference signal includes a voltage value and position information. A single bin is identified based on the position information of the reference signal. The identified bin is split into more than one bin based on the output of the memory cell and the voltage value of the reference signal. The newly split bins and all the other bins that were not split are assigned new bin indices.
    Type: Grant
    Filed: May 22, 2012
    Date of Patent: March 25, 2014
    Assignee: Marvell World Trade Ltd.
    Inventors: Zhengang Chen, Gregory Burd, Shashi Kiran Chilappagari, Xueshi Yang
  • Group based read reference voltage management in flash memory
    Patent number: 8675414
    Abstract: Apparatus, methods, and other embodiments associated with group based read reference voltage management in flash memory are described. According to one embodiment, an apparatus includes a program logic configured to program a cell in a flash memory device. The apparatus includes a read logic configured to read a cell in the flash memory device. A Vref memory is configured to store respective Vref values associated with respective groups of cells. The Vref values are used by the read logic for reading cells in the flash memory device. A cell is assigned to one of the groups of cells based, at least in part, on a time interval during which the cell is programmed by the program logic. The reader logic is configured to read a given cell using a Vref value associated with a group of cells to which the given cell is assigned.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: March 18, 2014
    Assignee: Marvell International Ltd.
    Inventors: Xueshi Yang, Gregory Burd
  • Reliability metrics management for soft decoding
    Patent number: 8665650
    Abstract: Embodiments provide a method for reading a target memory sector of a memory. The method comprises, based on read data corresponding to a plurality of memory sectors of the memory, estimating first one or more reference voltages and, using the first one or more reference voltages, performing a first read operation on the target memory sector. The method further comprises determining an error correcting code (ECC) decoding failure of the first read operation and, in response to determining the ECC decoding failure of the first read operation and based on read data corresponding to the target memory sector, updating the estimate of the first one or more reference voltages to generate second one or more reference voltages. The method also comprises using the second one or more reference voltages, performing a second read operation on the target memory sector.
    Type: Grant
    Filed: February 15, 2012
    Date of Patent: March 4, 2014
    Assignee: Marvell World Trade Ltd.
    Inventor: Xueshi Yang