Patents by Inventor Xumou Xu

Xumou Xu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8501395
    Abstract: Embodiments of the present invention relate to lithographic processes used in integrated circuit fabrication for improving line edge roughness (LER) and reduced critical dimensions (CD) for lines and/or trenches. Embodiments use the combinations of polarized light lithography, shrink coating processes, and double exposure processes to produce synergetic effects in the formation of trench structures having good resolution, reduced CDs, reduced pitch, and reduced LER in the lines and/or trenches of the patterned interconnect structures.
    Type: Grant
    Filed: June 3, 2008
    Date of Patent: August 6, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Huixiong Dai, Xumou Xu, Christopher S. Ngai
  • Patent number: 8293460
    Abstract: Methods to pattern features in a substrate layer by exposing a photoresist layer more than once. In one embodiment, a single reticle may be exposed more than once with an overlay offset implemented between successive exposures to reduce the half pitch of the reticle. In particular embodiments, these methods may be employed to reduce the half pitch of the features printed with 65 nm generation lithography equipment to achieve 45 nm lithography generation CD and pitch performance.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: October 23, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Hui W. Chen, Chorng-Ping Chang, Yongmei Chen, Huixiong Dai, Jiahua Yu, Susie X. Yang, Xumou Xu, Christopher D. Bencher, Raymond Hoiman Hung, Michael P. Duane, Christopher Siu Wing Ngai, Jen Shu, Kenneth MacWilliams
  • Publication number: 20090311635
    Abstract: Methods to pattern features in a substrate layer by exposing a photoresist layer more than once. In one embodiment, a single reticle may be exposed more than once with an overlay offset implemented between successive exposures to reduce the half pitch of the reticle. In particular embodiments, these methods may be employed to reduce the half pitch of the features printed with 65 nm generation lithography equipment to achieve 45 nm lithography generation CD and pitch performance.
    Type: Application
    Filed: December 19, 2008
    Publication date: December 17, 2009
    Inventors: HUI W. CHEN, CHORNG-PING CHANG, YONGMEI CHEN, HUIXIONG DAI, JIAHUA YU, SUSIE X. YANG, XUMOU XU, CHRISTOPHER D. BENCHER, RAYMOND HOIMAN HUNG, MICHAEL P. DUANE, CHRISTOPHER SIU WING NGAI, JEN SHU, KENNETH MACWILLIAMS
  • Publication number: 20090142926
    Abstract: Embodiments of the present invention relate to lithographic processes used in integrated circuit fabrication for improving line edge roughness (LER) and reduced critical dimensions (CD) for lines and/or trenches. Embodiments use the combinations of polarized light lithography, shrink coating processes, and double exposure processes to produce synergetic effects in the formation of trench structures having good resolution, reduced CDs, reduced pitch, and reduced LER in the lines and/or trenches of the patterned interconnect structures.
    Type: Application
    Filed: June 3, 2008
    Publication date: June 4, 2009
    Inventors: Huixiong Dai, Xumou Xu, Christopher S. Ngai