Patents by Inventor Xunyuan Zhang

Xunyuan Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240085628
    Abstract: Aspects described herein include an optical apparatus. The optical apparatus includes a first optical waveguide formed in a first semiconductor layer and a second optical waveguide formed in a second semiconductor layer and separated from the first optical waveguide by a dielectric layer. The first optical waveguide extends in a direction of an optical path. The first optical waveguide and the second optical waveguide are at least partly overlapping along the direction. At least the first optical waveguide has a first ridge extending along the direction. The first ridge defined between spacers having a predetermined width.
    Type: Application
    Filed: November 13, 2023
    Publication date: March 14, 2024
    Inventor: Xunyuan ZHANG
  • Patent number: 11906824
    Abstract: Embodiments provide for an optical modulator, comprising: a lower guide, comprising: a lower hub, made of monocrystalline silicon; and a lower ridge, made of monocrystalline silicon that extends in a first direction from the lower hub; an upper guide, including: an upper hub; and an upper ridge, made of monocrystalline silicon that extends in a second direction, opposite of the first direction, from the upper hub and is aligned with the lower ridge; and a gate oxide layer separating the lower ridge from the upper ridge and defining a waveguide region with the lower guide and the upper guide.
    Type: Grant
    Filed: March 2, 2023
    Date of Patent: February 20, 2024
    Assignee: Cisco Technology, Inc.
    Inventors: Xunyuan Zhang, Vipulkumar K. Patel, Prakash B. Gothoskar, Ming Gai Stanley Lo
  • Patent number: 11860417
    Abstract: Aspects described herein include a method of fabricating an optical apparatus. The method comprises etching a plurality of trenches partly through a first optical waveguide formed in a first semiconductor layer, wherein a first ridge is formed in the first optical waveguide between adjacent trenches of the plurality of trenches. The method further comprises conformally depositing a spacer layer above the first optical waveguide, wherein spacers are formed on sidewalls of each trench of the plurality of trenches. The method further comprises etching through the spacer layer to expose a respective bottom of each trench, wherein, for each respective bottom, a width of the respective bottom is defined by the spacers formed on the sidewalls of the trench corresponding to the respective bottom. The method further comprises depositing a first dielectric layer above the first optical waveguide, wherein dielectric material extends to the respective bottom of each trench.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: January 2, 2024
    Assignee: Cisco Technology, Inc.
    Inventor: Xunyuan Zhang
  • Publication number: 20230290898
    Abstract: The embodiments of the present disclosure describe a stressed Ge PD and fabrications techniques for making the same. In one embodiment, a stressor material is deposited underneath an already formed Ge PD. To do so, wafer bonding can be used to bond the wafer containing the Ge PD to a second, handler wafer. Doing so provides support to remove the substrate of the wafer so that a stressor material (e.g., silicon nitride, diamond-like carbon, or silicon-germanium) can be disposed underneath the Ge PD. The stress material induces a stress or strain in the crystal lattice of the Ge which changes its bandgap and improves its responsivity.
    Type: Application
    Filed: May 16, 2023
    Publication date: September 14, 2023
    Inventors: Xunyuan ZHANG, Li LI, Prakash B. GOTHOSKAR, Soha NAMNABAT
  • Patent number: 11754784
    Abstract: Embodiments presented in this disclosure generally relate to an optical device having a grating coupler for redirection of optical signals. One embodiment includes a grating coupler. The grating coupler generally includes a waveguide layer, a thickness of a waveguide layer portion of the waveguide layer being tapered, the thickness defining a direction, and a grating layer disposed above the waveguide layer and perpendicular to the direction where at least a grating layer portion of the grating layer overlaps the waveguide layer portion of the waveguide layer along the direction. Some embodiments are directed to grating coupler implemented with material layers above and a reflector layer below a grating layer, facilitating redirection and confinement of light that improves coupling loss and bandwidth. The material layers and reflector layer above and below the grating layer may be implemented with or without the waveguide layer being tapered.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: September 12, 2023
    Assignee: Cisco Technology, Inc.
    Inventors: Tao Ling, Shiyi Chen, Xunyuan Zhang, Prakash B. Gothoskar
  • Patent number: 11742451
    Abstract: The embodiments of the present disclosure describe a stressed Ge PD and fabrications techniques for making the same. In one embodiment, a stressor material is deposited underneath an already formed Ge PD. To do so, wafer bonding can be used to bond the wafer containing the Ge PD to a second, handler wafer. Doing so provides support to remove the substrate of the wafer so that a stressor material (e.g., silicon nitride, diamond-like carbon, or silicon-germanium) can be disposed underneath the Ge PD. The stress material induces a stress or strain in the crystal lattice of the Ge which changes its bandgap and improves its responsivity.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: August 29, 2023
    Assignee: Cisco Technology, Inc.
    Inventors: Xunyuan Zhang, Li Li, Prakash B. Gothoskar, Soha Namnabat
  • Publication number: 20230243718
    Abstract: Electrical test of optical components via metal-insulator-semiconductor capacitor structures is provided via a plurality of optical devices including a first material embedded in a second material, wherein each optical device is associated with a different thickness range of a plurality of thickness ranges for the first material; a first capacitance measurement point including the first material embedded in the second material; and a second capacitance measurement point including a region from which the first material has been replaced with the second material.
    Type: Application
    Filed: April 7, 2023
    Publication date: August 3, 2023
    Inventors: Xunyuan ZHANG, Ravi S. TUMMIDI, Tony P. POLOUS, Mark A. WEBSTER
  • Publication number: 20230204987
    Abstract: Embodiments provide for an optical modulator, comprising: a lower guide, comprising: a lower hub, made of monocrystalline silicon; and a lower ridge, made of monocrystalline silicon that extends in a first direction from the lower hub; an upper guide, including: an upper hub; and an upper ridge, made of monocrystalline silicon that extends in a second direction, opposite of the first direction, from the upper hub and is aligned with the lower ridge; and a gate oxide layer separating the lower ridge from the upper ridge and defining a waveguide region with the lower guide and the upper guide.
    Type: Application
    Filed: March 2, 2023
    Publication date: June 29, 2023
    Inventors: Xunyuan ZHANG, Vipulkumar K. PATEL, Prakash B. GOTHOSKAR, Ming Gai Stanley LO
  • Patent number: 11686648
    Abstract: Electrical test of optical components via metal-insulator-semiconductor capacitor structures is provided via a plurality of optical devices including a first material embedded in a second material, wherein each optical device is associated with a different thickness range of a plurality of thickness ranges for the first material; a first capacitance measurement point including the first material embedded in the second material; and a second capacitance measurement point including a region from which the first material has been replaced with the second material.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: June 27, 2023
    Assignee: Cisco Technology, Inc.
    Inventors: Xunyuan Zhang, Ravi S. Tummidi, Tony P. Polous, Mark A. Webster
  • Patent number: 11619838
    Abstract: Embodiments provide for an optical modulator, comprising: a lower guide, comprising: a lower hub, made of monocrystalline silicon; and a lower ridge, made of monocrystalline silicon that extends in a first direction from the lower hub; an upper guide, including: an upper hub; and an upper ridge, made of monocrystalline silicon that extends in a second direction, opposite of the first direction, from the upper hub and is aligned with the lower ridge; and a gate oxide layer separating the lower ridge from the upper ridge and defining a waveguide region with the lower guide and the upper guide.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: April 4, 2023
    Assignee: Cisco Technology, Inc.
    Inventors: Xunyuan Zhang, Vipulkumar K. Patel, Prakash B. Gothoskar, Ming Gai Stanley Lo
  • Publication number: 20230074516
    Abstract: Embodiments presented in this disclosure generally relate to an optical device having a grating coupler for redirection of optical signals. One embodiment includes a grating coupler. The grating coupler generally includes a waveguide layer, a thickness of a waveguide layer portion of the waveguide layer being tapered, the thickness defining a direction, and a grating layer disposed above the waveguide layer and perpendicular to the direction where at least a grating layer portion of the grating layer overlaps the waveguide layer portion of the waveguide layer along the direction. Some embodiments are directed to grating coupler implemented with material layers above and a reflector layer below a grating layer, facilitating redirection and confinement of light that improves coupling loss and bandwidth. The material layers and reflector layer above and below the grating layer may be implemented with or without the waveguide layer being tapered.
    Type: Application
    Filed: September 8, 2021
    Publication date: March 9, 2023
    Inventors: Tao LING, Shiyi CHEN, Xunyuan ZHANG, Prakash B. GOTHOSKAR
  • Publication number: 20230030971
    Abstract: Embodiments presented in this disclosure generally relate to optical signal processing. More specifically, embodiments disclosed herein are directed to a semiconductor-insulator-semiconductor capacitor (SISCAP) modulator. One embodiment includes an optical modulator having a capacitive element configured to modulate an optical signal. The capacitive element includes a single-crystal semiconductor layer, a silicon germanium layer, and a dielectric region between the single-crystal semiconductor layer and the silicon germanium layer.
    Type: Application
    Filed: July 28, 2021
    Publication date: February 2, 2023
    Inventors: Vipulkumar K. PATEL, Ming Gai Stanley LO, Xunyuan ZHANG
  • Publication number: 20230022612
    Abstract: Electrical test of optical components via metal-insulator-semiconductor capacitor structures is provided via a plurality of optical devices including a first material embedded in a second material, wherein each optical device is associated with a different thickness range of a plurality of thickness ranges for the first material; a first capacitance measurement point including the first material embedded in the second material; and a second capacitance measurement point including a region from which the first material has been replaced with the second material.
    Type: Application
    Filed: July 23, 2021
    Publication date: January 26, 2023
    Inventors: Xunyuan ZHANG, Ravi S. TUMMIDI, Tony P. POLOUS, Mark A. WEBSTER
  • Publication number: 20220165907
    Abstract: The embodiments of the present disclosure describe a stressed Ge PD and fabrications techniques for making the same. In one embodiment, a stressor material is deposited underneath an already formed Ge PD. To do so, wafer bonding can be used to bond the wafer containing the Ge PD to a second, handler wafer. Doing so provides support to remove the substrate of the wafer so that a stressor material (e.g., silicon nitride, diamond-like carbon, or silicon-germanium) can be disposed underneath the Ge PD. The stress material induces a stress or strain in the crystal lattice of the Ge which changes its bandgap and improves its responsivity.
    Type: Application
    Filed: November 24, 2020
    Publication date: May 26, 2022
    Inventors: Xunyuan ZHANG, Li LI, Prakash B. GOTHOSKAR, Soha NAMNABAT
  • Patent number: 11114338
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to fully aligned via structures and methods of manufacture. The structure includes: a plurality of minimum ground rule conductive structures formed in a dielectric material each of which comprises a recessed conductive material therein; at least one conductive structure formed in the dielectric material which is wider than the plurality of minimum ground rule conductive structures; an etch stop layer over a surface of the dielectric layer with openings to expose the conductive material of the least one conductive structure and the recessed conductive material of a selected minimum ground rule conductive structure; and an upper conductive material fully aligned with and in direct electrical contact with the at least one conductive structure and the selected minimum ground rule conductive structure, through the openings of the etch stop layer.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: September 7, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Nicholas V. Licausi, Xunyuan Zhang
  • Publication number: 20210263351
    Abstract: Embodiments provide for an optical modulator, comprising: a lower guide, comprising: a lower hub, made of monocrystalline silicon; and a lower ridge, made of monocrystalline silicon that extends in a first direction from the lower hub; an upper guide, including: an upper hub; and an upper ridge, made of monocrystalline silicon that extends in a second direction, opposite of the first direction, from the upper hub and is aligned with the lower ridge; and a gate oxide layer separating the lower ridge from the upper ridge and defining a waveguide region with the lower guide and the upper guide.
    Type: Application
    Filed: May 7, 2021
    Publication date: August 26, 2021
    Inventors: Xunyuan ZHANG, Vipulkumar K. PATEL, Prakash B. GOTHOSKAR, Ming Gai Stanley LO
  • Patent number: 11036069
    Abstract: Embodiments provide for an optical modulator, comprising: a lower guide, comprising: a lower hub, made of monocrystalline silicon; and a lower ridge, made of monocrystalline silicon that extends in a first direction from the lower hub; an upper guide, including: an upper hub; and an upper ridge, made of monocrystalline silicon that extends in a second direction, opposite of the first direction, from the upper hub and is aligned with the lower ridge; and a gate oxide layer separating the lower ridge from the upper ridge and defining a waveguide region with the lower guide and the upper guide.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: June 15, 2021
    Assignee: Cisco Technology, Inc.
    Inventors: Xunyuan Zhang, Vipulkumar K. Patel, Prakash B. Gothoskar, Ming Gai Stanley Lo
  • Patent number: 11022757
    Abstract: Embodiments herein describe a photonic platform where an AR coating is disposed between an optical grating and a semiconductor substrate. In one embodiment, the optical grating is disposed within an insulative layer. A first side of the insulative layer provides an optical interface where an external optical source can transmit an optical signal into, or a receive an optical signal from, the grating. A second, opposite side of the insulative layer contacts the AR coating. When the external optical source transmits light through the first side of the insulative layer, some of the light passes through the grating and reaches the AR coating. The AR coating prevents this light from being reflected back to the grating by the semiconductor layer which can cause interference that varies the coupling efficiency of the grating.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: June 1, 2021
    Assignee: Cisco Technology, Inc.
    Inventors: Xunyuan Zhang, Shiyi Chen, Tao Ling, Prakash B. Gothoskar
  • Publication number: 20210157033
    Abstract: Embodiments herein describe a photonic platform where an AR coating is disposed between an optical grating and a semiconductor substrate. In one embodiment, the optical grating is disposed within an insulative layer. A first side of the insulative layer provides an optical interface where an external optical source can transmit an optical signal into, or a receive an optical signal from, the grating. A second, opposite side of the insulative layer contacts the AR coating. When the external optical source transmits light through the first side of the insulative layer, some of the light passes through the grating and reaches the AR coating. The AR coating prevents this light from being reflected back to the grating by the semiconductor layer which can cause interference that varies the coupling efficiency of the grating.
    Type: Application
    Filed: November 26, 2019
    Publication date: May 27, 2021
    Inventors: Xunyuan ZHANG, Shiyi CHEN, Tao LING, Prakash B. GOTHOSKAR
  • Patent number: RE49820
    Abstract: An approach for forming a semiconductor device is provided. In general, the device is formed by providing a metal layer, a cap layer over the metal layer, and an ultra low k layer over the cap layer. A via is then formed through the ultra low k layer and the cap layer. Once the via is formed, a barrier layer (e.g., cobalt (Co), tantalum (Ta), cobalt-tungsten-phosphide (CoWP), or other metal capable of acting as a copper (CU) diffusion barrier) is selectively applied to a bottom surface of the via. A liner layer (e.g., manganese (MN) or aluminum (AL)) is then applied to a set of sidewalls of the via. The via may then be filled with a subsequent metal layer (with or without a seed layer), and the device may the then be further processed (e.g., annealed).
    Type: Grant
    Filed: August 31, 2019
    Date of Patent: January 30, 2024
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Larry Zhao, Ming He, Xunyuan Zhang, Sean Xuan Lin