Patents by Inventor Y.Y. Peng

Y.Y. Peng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • MACHINE LEARNING ON OVERLAY MANAGEMENT
    Publication number: 20230223287
    Abstract: The current disclosure describes techniques for managing vertical alignment or overlay in semiconductor manufacturing using machine learning. Alignments of interconnection features in a fan-out WLP process are evaluated and managed through the disclosed techniques. Big data and neural networks system are used to correlate the overlay error source factors with overlay metrology categories. The overlay error source factors include tool related overlay source factors, wafer or die related overlay source factors and processing context related overlay error source factors.
    Type: Application
    Filed: March 14, 2023
    Publication date: July 13, 2023
    Inventors: Tzu-Cheng LIN, Y.Y. PENG, Jerry WANG, Kewei ZUO, Chien Rhone WANG
  • Machine learning on overlay management
    Patent number: 11626304
    Abstract: The current disclosure describes techniques for managing vertical alignment or overlay in semiconductor manufacturing using machine learning. Alignments of interconnection features in a fan-out WLP process are evaluated and managed through the disclosed techniques. Big data and neural networks system are used to correlate the overlay error source factors with overlay metrology categories. The overlay error source factors include tool related overlay source factors, wafer or die related overlay source factors and processing context related overlay error source factors.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: April 11, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tzu-Cheng Lin, Y. Y. Peng, Jerry Wang, Kewei Zuo, Chien Rhone Wang
  • MACHINE LEARNING ON OVERLAY MANAGEMENT
    Publication number: 20210175105
    Abstract: The current disclosure describes techniques for managing vertical alignment or overlay in semiconductor manufacturing using machine learning. Alignments of interconnection features in a fan-out WLP process are evaluated and managed through the disclosed techniques. Big data and neural networks system are used to correlate the overlay error source factors with overlay metrology categories. The overlay error source factors include tool related overlay source factors, wafer or die related overlay source factors and processing context related overlay error source factors.
    Type: Application
    Filed: February 18, 2021
    Publication date: June 10, 2021
    Inventors: Tzu-Cheng LIN, Y.Y. PENG, Jerry WANG, Kewei ZUO, Chien Rhone WANG
  • Machine learning on overlay virtual metrology
    Patent number: 10964566
    Abstract: The current disclosure describes techniques for managing vertical alignment or overlay in semiconductor manufacturing using machine learning. Alignments of interconnection features in a fan-out WLP process are evaluated and managed through the disclosed techniques. Big data and neural networks system are used to correlate the overlay error source factors with overlay metrology categories. The overlay error source factors include tool related overlay source factors, wafer or die related overlay source factors and processing context related overlay error source factors.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: March 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Go., Ltd.
    Inventors: Tzu-Cheng Lin, Y.Y. Peng, Jerry Wang, Kewei Zuo, Chien Rhone Wang
  • MACHINE LEARNING ON OVERLAY VIRTUAL METROLOGY
    Publication number: 20200006102
    Abstract: The current disclosure describes techniques for managing vertical alignment or overlay in semiconductor manufacturing using machine learning. Alignments of interconnection features in a fan-out WLP process are evaluated and managed through the disclosed techniques. Big data and neural networks system are used to correlate the overlay error source factors with overlay metrology categories. The overlay error source factors include tool related overlay source factors, wafer or die related overlay source factors and processing context related overlay error source factors.
    Type: Application
    Filed: May 7, 2019
    Publication date: January 2, 2020
    Inventors: Tzu-Cheng Lin, Y.Y. Peng, Jerry Wang, Kewei Zuo, Chien Rhone Wang