Abstract: The present disclosure provides one embodiment of a semiconductor structure that includes a first metal layer formed on a semiconductor substrate, wherein the first metal layer includes a first metal feature in a first region and a second metal feature in a second region; a second metal layer disposed on the first metal layer, wherein the second metal layer includes a third metal feature in the first region and a fourth metal feature in a second region; a magneto-resistive memory device sandwiched between the first metal feature and the third metal feature; and a capacitor sandwiched between the second metal feature and the fourth metal feature.

Abstract: A display device of the present invention includes a light source apparatus and a rear light transmitting module disposed opposite a first light emitting surface of the light source apparatus. The rear light transmitting module includes a first transmitting layer and a second transmitting layer. The first transmitting layer has a plurality of first prisms arranged side by side and respectively protruding toward the first light emitting surface. The second transmitting layer is overlapped with the first transmitting layer on one side thereof opposite the first light emitting surface, and has a plurality of second prisms arranged side by side and respectively protruding toward the first transmitting layer. A vertical projection range of the first prisms on the first light emitting surface is misaligned with a vertical projection range of the second prisms on the first light emitting surface.

Abstract: The present invention provides a display device including a display panel and a haze layer. The display panel includes a plurality of pixels and a color determining surface. The orthogonal projection of each of the plurality of pixels onto the color determining surface forms a plurality of adjacent pixel ranges. The haze layer is disposed on a side of the color determining surface and has a haze surface facing away from the color determining surface. The haze layer has a scattering coefficient ranging from ?1.4 to 0. The haze surface includes a first location corresponding to the center of the first pixel range, and a second location corresponding to a location away from the first edge towards the second pixel range wherein the distance therebetween ranges from 87 ?m to 174 ?m.

Abstract: The present disclosure relates to a structure and method for embedding a non-volatile memory (NVM) in a HKMG (high-? metal gate) integrated circuit which includes a high-voltage (HV) HKMG transistor. NVM devices (e.g., flash memory) are operated at high voltages for its read and write operations and hence a HV device is necessary for integrated circuits involving non-volatile embedded memory and HKMG logic circuits. Forming a HV HKMG circuit along with the HKMG periphery circuit reduces the need for additional boundaries between the HV transistor and rest of the periphery circuit. This method further helps reduce divot issue and reduce cell size.

Abstract: The present disclosure relates to a structure and method for embedding a non-volatile memory (NVM) in a HKMG (high-? metal gate) integrated circuit which includes a high-voltage (HV) HKMG transistor. NVM devices (e.g., flash memory) are operated at high voltages for its read and write operations and hence a HV device is necessary for integrated circuits involving non-volatile embedded memory and HKMG logic circuits. Forming a HV HKMG circuit along with the HKMG periphery circuit reduces the need for additional boundaries between the HV transistor and rest of the periphery circuit. This method further helps reduce divot issue and reduce cell size.

Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a floating gate test device with a cell-like top layout, as well as a method for forming the IC. In some embodiments, the IC comprises a semiconductor substrate and the floating gate test device. The floating gate test device is on the semiconductor substrate, and comprises a floating gate electrode and a control gate electrode overlying the floating gate electrode. The floating gate electrode and the control gate electrode partially define an array of islands, and further partially define a plurality of bridges interconnecting the islands. The islands and the bridges define the cell-like top layout and may, for example, prevent process-induced damage to the floating gate test device.

Abstract: The present invention provides a display device including a display panel and a haze layer. The display panel includes a plurality of pixels and a color determining surface. The orthogonal projection of each of the plurality of pixels onto the color determining surface forms a plurality of adjacent pixel ranges. The haze layer is disposed on a side of the color determining surface and has a haze surface facing away from the color determining surface. The haze layer has a scattering coefficient ranging from ?1.4 to 0. The haze surface includes a first location corresponding to the center of the first pixel range, and a second location corresponding to a location away from the first edge towards the second pixel range wherein the distance therebetween ranges from 87 ?m to 174 ?m.

Abstract: Methods for forming a magneto-resistive memory device and a capacitor in an interconnect structure are disclosed herein. An exemplary method includes forming a first level interconnect metal layer and a second level interconnect metal layer of an interconnect structure. The method further includes simultaneously forming a first plurality of layers in a first region of the interconnect structure and a second plurality of layers in a second region of the interconnect structure, wherein the first plurality of layers and the second plurality of layers are disposed between the first level interconnect metal layer and the second level interconnect metal layer. The first plurality of layers is configured as a magneto-resistive memory device. The second plurality of layers is configured as the capacitor. The magneto-resistive memory device and the capacitor are each coupled to the first level interconnect metal layer and the second level interconnect metal layer.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a split gate stack having a main gate and a select gate and forming a logic gate stack having a logic gate over a semiconductor substrate. The main gate and the logic gate is respectively replaced with a metal memory gate and a metal logic gate, in which the main gate and the logic gate are replaced simultaneously.

Abstract: An integrated circuit structure includes a plurality of flash memory cells forming a memory array, wherein each of the plurality of flash memory cells includes a select gate and a memory gate. A select gate electrode includes a first portion including polysilicon, wherein the first portion forms select gates of a column of the memory array, and a second portion electrically connected to the first portion, wherein the second portion includes a metal. A memory gate electrode has a portion forming memory gates of the column of the memory array.

Abstract: A semiconductor device includes a substrate, at least one split gate memory device, and at least one logic device. The split gate memory device is disposed on the substrate. The logic device is disposed on the substrate. A select gate or a main gate of the split gate memory device and a logic gate of the logic device are both made of metal, and the other gate of the split gate memory device is made of nonmetal.

Abstract: The present disclosure relates a method for manufacturing an integrated circuit. In some embodiments, a semiconductor substrate is provided and made up of a memory array region and a boundary region surrounding the memory array region. A hard mask layer is formed over the memory array region and the boundary region. The hard mask layer is patterned to form a boundary hard mask having one or more slots to expose some portions of the boundary region while the remaining regions of the boundary region are covered by the boundary hard mask. A floating gate layer is formed within the memory array region and extending over the hard mask layer. Then, a planarization is performed to reduce a height of the floating gate layer and form a plurality of floating gates.

Abstract: The present disclosure relates to a structure and method for embedding a non-volatile memory (NVM) in a HKMG (high-? metal gate) integrated circuit which includes a high-voltage (HV) HKMG transistor. NVM devices (e.g., flash memory) are operated at high voltages for its read and write operations and hence a HV device is necessary for integrated circuits involving non-volatile embedded memory and HKMG logic circuits. Forming a HV HKMG circuit along with the HKMG periphery circuit reduces the need for additional boundaries between the HV transistor and rest of the periphery circuit. This method further helps reduce divot issue and reduce cell size.

Abstract: Some embodiments of the present disclosure provide an integrated circuit (IC) for an embedded flash memory device. The IC includes a flash memory cell having a memory cell gate. A silicide contact pad is arranged in a recess of the memory cell gate. A top surface of the silicide contact pad is recessed relative to a top surface of the memory cell gate. Dielectric side-wall spacers extend along sidewalls of the recess from the top surface of the memory cell gate to the top surface of the silicide contact pad.

Abstract: The present disclosure relates a method for manufacturing an integrated circuit. In some embodiments, a semiconductor substrate is provided and made up of a memory array region and a boundary region surrounding the memory array region. A hard mask layer is formed over the memory array region and the boundary region. The hard mask layer is patterned to form a boundary hard mask having one or more slots to expose some portions of the boundary region while the remaining regions of the boundary region are covered by the boundary hard mask. A floating gate layer is formed within the memory array region and extending over the hard mask layer. Then, a planarization is performed to reduce a height of the floating gate layer and form a plurality of floating gates.

Abstract: The present disclosure relates to a structure and method for embedding a non-volatile memory (NVM) in a HKMG (high-? metal gate) integrated circuit which includes a high voltage (HV) HKMG transistor. NVM devices (e.g., flash memory) are operated at high voltages for its read and write operations and hence a HV device is necessary for integrated circuits involving non-volatile embedded memory and HKMG logic circuits. Forming a HV HKMG circuit along with the HKMG periphery circuit reduces the need for additional boundaries between the HV transistor and rest of the periphery circuit. This method further helps reduce divot issue and reduce cell size.

Abstract: The present disclosure relates an integrated circuit (IC) for an embedded flash memory device. In some embodiments, the IC includes a memory array region and a boundary region surrounding the memory array region disposed over a semiconductor substrate. A hard mask is disposed at the memory array region comprising a plurality of discrete portions. The hard mask is disposed under a control dielectric layer of the memory array region.

Abstract: An integrated circuit structure includes a plurality of flash memory cells forming a memory array, wherein each of the plurality of flash memory cells includes a select gate and a memory gate. A select gate electrode includes a first portion including polysilicon, wherein the first portion forms select gates of a column of the memory array, and a second portion electrically connected to the first portion, wherein the second portion includes a metal. A memory gate electrode has a portion forming memory gates of the column of the memory array.

Abstract: The present disclosure relates to a structure and method for reducing contact over-etching and high contact resistance (Rc) on an embedded flash memory HKMG integrated circuit. In one embodiment, an STI region underlying a memory contact pad region is recessed to make the STI surface substantially co-planar with the rest of the semiconductor substrate. The recess allows formation of thicker memory contact pad structures. The thicker polysilicon on these contact pad structures prevents contact over-etching and thus reduces the Rc of contacts formed thereon.

Abstract: The present disclosure relates to a structure and method for reducing CMP dishing in integrated circuits. In some embodiments, the structure has a semiconductor substrate with an embedded memory region and a periphery region. one or more dummy structures are formed between the memory region and the periphery region. Placement of the dummy structures between the embedded memory region and the periphery region causes the surface of a deposition layer therebetween to become more planar after being polished without resulting in a dishing effect. The reduced recess reduces metal residue formation and thus leakage and shorting of current due to metal residue. Further, less dishing will reduce the polysilicon loss of active devices. In some embodiments, one of the dummy structures is formed with an angled sidewall which eliminates the need for a boundary cut etch process.