Abstract: The present invention is directed to a semiconductor device formed on a silicon substrate that has at least one inductor integrated therewith. The inductor is formed on a region of porous silicon formed in the substrate. The porous silicon reduces the capacitive and inductive coupling of the inductor to the substrate. Therefore, the integrated inductors of the present invention are capable of having a higher inductance at higher resonance frequencies (i.e. 2 GHz or greater) than conventional inductors. Devices with inductors that operate at these frequencies are desirable for wireless applications. The present invention is also directed to a process for fabricating the device in which the porous silicon is formed using an annodization technique, and wherein the porous silicon so formed is maintained in an essentially unoxidized state throughout the remainder of the process.

Abstract: A heterostructure includes a stained epitaxial layer of either silicon or germanium that is located overlying a silicon substrate, with a spatially graded Ge.sub.x Si.sub.1-x epitaxial layer overlain by a ungraded Ge.sub.x.sbsb.0 Si.sub.1-x.sbsb.0 intervening between the silicon substrate and the strained layer. Such a heterostructure can serve as a foundation for such devices as surface emitting LEDs, either n-channel or p-channel silicon-based MODFETs, and either n-channel or p-channel silicon-based MOSFETs.

Abstract: The invention is predicated upon the discovery by applicants that exposure of a Ge surface to arsenic produces a drastic change in the step structure of the Ge surface. Subsequent exposure to Ga and growth of GaAs produces three-dimensional growth and a high threading dislocation density at the GaAs/Ge interface. However exposure of the Ge surface to Ga does not substantially change the Ge step structure, and subsequent growth of GaAs is two-dimensional with little increase in threading dislocation density. Thus a high quality semiconductor heterostructure of gallium arsenide on germanium can be made by exposing a germanium surface in an environment substantially free of arsenic, depositing a layer of gallium on the surface and then growing a layer of gallium arsenide. The improved method can be employed to make a variety of optoelectronic devices such as light-emitting diodes.

Abstract: An integrated photodiode is formed by providing a silicon substrate with a deep recessed tub in excess of about 20 microns, forming an isolated p-n junction on the peripheral tub surfaces, and selectively epitaxially filling the tub with intrinsic silicon. A desired monolithic integrated circuit is fabricated outside the tub periphery using conventional VLSI techniques. A photodiode electrode structure within the tub periphery can be fabricated at the same time as other monolithic circuit components are formed.

Abstract: The present invention is predicated upon the discovery by applicants that by growing germanium-silicon alloy at high temperatures in excess of about 850.degree. C. and increasing the germanium content at a gradient of less than about 25% per micrometer, one can grow on silicon large area heterostructures of graded Ge.sub.x Si.sub.1-x alloy having a low level of threading dislocation defects. With low concentrations of germanium 0.10.ltoreq..times..ltoreq.0.50), the heterolayer can be used as a substrate for growing strained layer silicon devices such as MODFETS. With high concentrations of Ge (0.65.ltoreq..times..ltoreq.1.00) the heterolayer can be used on silicon substrates as a buffer layer for indium gallium phosphide devices such as light emitting diodes and lasers. At concentrations of pure germanium (X=1.00), the heterolayer can be used for GaAs or GaAs/AlGaAs devices.

Abstract: An integrated photodiode is formed by providing a silicon substrate with a deep recessed tub in excess of about 20 microns, forming an isolated p-n junction on the peripheral tub surfaces, and selectively epitaxially filling the tub with intrinsic silicon. A desired monolithic integrated circuit is fabricated outside the tub periphery using conventional VLSI techniques. A photodiode electrode structure within the tub periphery can be fabricated at the same time as other monolithic circuit components are formed.

Abstract: A vertical-cavity surface-emitting semiconductive laser has non-epitaxial multilayered dielectric reflectors located on both its top and its bottom surfaces, in order to facilitate fabrication of the reflectors and achieve high optical cavity gain and low electrical power dissipation.

Abstract: In a vertical semiconductor laser, the top mirror is composed of alternating layers of lattice-mismatched semiconductors. Quantum reflections and other charge transport barriers for majority carriers at the interface, and hence electrical resistance and power dissipation, are reduced by choosing the lattice-mismatched semiconductor materials in such a manner as to align their band edges for majority carriers. On the other hand, the semiconductor materials are selected to supply relatively large refractive index differences, and hence relatively large optical reflections, at their interfaces. The lattice-mismatching may also produce vertical thread dislocations through the stack, which increase the electrical conductivity.

Abstract: A vertical laser is typically formed by successive horizontal layers, epitaxially grown on a substrate, suitable for forming a bottom mirror, a bottom cladding layer, an active region, a top cladding layer, and a top mirror. In prior art, one of a pair of electrodes for enabling electrical pumping the laser--the "top" electrode--is attached to the top surface of the top mirror, whereby undesirably large amounts of heat are generated because of the relatively high impedance of the top mirror. To reduce this heat generation, the laser is redesigned to enable the top electrode to make lateral contact with the top cladding layer, whereby the impedance and hence the power loss are reduced.