Abstract: A pretreatment liquid for water-based pigment textile printing is disclosed, which includes: 1 wt % to 30 wt % of aqueous non-ionic polyurethane; 1 wt % to 20 wt % of a metal salt; 0.1 wt % to 10 wt % of a melamine resin; and the balance being a solvent. A method for forming a pattern on a textile using the aforesaid pretreatment liquid is also disclosed.

Abstract: A pretreatment liquid for water-based pigment textile printing is disclosed, which includes: 1 wt % to 30 wt % of aqueous non-ionic polyurethane; 1 wt % to 20 wt % of a metal salt; 0.1 wt % to 10 wt % of a melamine resin; and the balance being a solvent. A method for forming a pattern on a textile using the aforesaid pretreatment liquid is also disclosed.

Abstract: An ultra-high whiteness aqueous white color paste for digital textile printing ink is provided, which comprises: 40 wt % to 70 wt % of TiO2 powders; 1 wt % to 5 wt % of a wetting agent; 2 wt % to 12 wt % of a dispersant; and rest of water. Herein, the TiO2 powders are rutile TiO2 powders, the wetting agent is a fatty acid derivative, and the dispersant is an acrylic acid copolymer. In addition, the present disclosure thrther provides an ink composition using the aforesaid ultra-high whiteness aqueous white color paste.

Abstract: A multi-time programmable (MTP) memory includes a tunneling dielectric layer, a floating gate, an inter-gate dielectric layer and a control gate. The tunneling dielectric layer is disposed on a substrate. The floating gate is disposed on the tunneling dielectric layer. The inter-gate dielectric layer is disposed on the floating gate, and a thickness of the inter-gate dielectric layer at edges of the floating gate is larger than a thickness of the inter-gate dielectric layer in a central portion of the floating gate. The control gate is disposed on the inter-gate dielectric layer.

Abstract: A substrate is provided, and a sacrificial pattern having an opening partially exposing a high voltage device region is formed on the substrate. Subsequently, a gate oxide layer is formed in the opening, and the sacrificial pattern is removed. A gate electrode, and two heavily doped regions are formed. Than, a salicidation process is carried out to form salicides on the surface of the gate electrode and the heavily doped regions.

Abstract: A multi-time programmable (MTP) memory includes a tunneling dielectric layer, a floating gate, an inter-gate dielectric layer and a control gate. The tunneling dielectric layer is disposed on a substrate. The floating gate is disposed on the tunneling dielectric layer. The inter-gate dielectric layer is disposed on the floating gate, and a thickness of the inter-gate dielectric layer at edges of the floating gate is larger than a thickness of the inter-gate dielectric layer in a central portion of the floating gate. The control gate is disposed on the inter-gate dielectric layer.