Abstract: A semiconductor device includes a substrate having a logic region and a magnetoresistive random access memory (MRAM) region, a MTJ on the MRAM region, a metal interconnection on the MTJ, and a blocking layer on the metal interconnection. Preferably, the blocking layer includes a stripe pattern according to a top view and the blocking layer could include metal or a dielectric layer.

Abstract: The present invention provides a control module and a control method thereof for an SDRAM. The control module includes at least one register and a controller. The controller is configured to: control the SDRAM to switch from a bus data access mode to a dynamic pin (DPIN) operating mode; setting value of the at least one register under the DPIN operating mode; and control the SDRAM according to the value of the at least one register.

Abstract: The present disclosure provides a circuit and a method thereof for setting an SDRAM. The circuit includes at least one register and a controller circuit. The controller circuit is configured to: control the SDRAM to switch to an initialization setting mode, wherein the initialization setting mode is utilized for initialing the SDRAM; set value of the at least one register under the initialization setting mode; and set the SDRAM according to the value of the at least one register.

Abstract: The present disclosure provides a control module and a control method thereof for an SDRAM. The control module includes a register and a controller. The controller is configured to: select a first command, wherein the first command includes at least two first memory commands; execute one of the at least two first memory commands; store an un-executed memory command of the at least two first memory commands in a register and back the un-executed memory command up as at least one first back-up memory command; select a second command, wherein the first command and the second command are stored in different memory bank groups; and execute the second command.

Abstract: The present invention provides a. control module and a control method thereof for an SDRAM. The control module includes at least one register and a controller. The controller is configured to: control the SDRAM to switch from a bus data access mode to a dynamic pin (DPIN) operating mode; setting value of the at least one register under the DPIN operating mode; and control the SDRAM according to the value of the at least one register.

Abstract: A memory system includes a memory controller, a first memory, and a second memory. The memory controller has a command address port, a chip select port, a first data port, and a second data port. The first memory is coupled to the command address port, the chip select port, and the first data port, and the second memory is coupled to the command address port, the chip select port, and the second data port. The capacity of the second memory is greater than the capacity of the first memory. The memory controller controls the first memory and the second memory simultaneously through the command address port and the chip select port.

Abstract: A memory system includes a memory controller, a first memory, and a second memory. The memory controller has a command address port, a chip select port, a first data port, and a second data port. The first memory is coupled to the command address port, the chip select port, and the first data port, and the second memory is coupled to the command address port, the chip select port, and the second data port. The capacity of the second memory is greater than the capacity of the first memory. The memory controller controls the first memory and the second memory simultaneously through the command address port and the chip select port.

Abstract: A method for resetting a memory in the computer system includes turning on the computer system, and a memory controller of the computer system executing a boot code to initialize the memory. After the memory controller executes the boot code, the memory controller updates a programmable initialization code according to the boot code to generate an updated programmable initialization code. After resetting the computer system, the memory controller executes the updated programmable initialization code to restore the memory back to a default state. After the memory is restored to the default state, the memory controller executes the boot code to initialize the memory again. After the memory is initialized, the memory controller controls the memory to perform a normal operation.

Abstract: This invention discloses a memory control circuit and a method thereof. The memory control method includes the steps of: transmitting a first clock to a serial peripheral interface (SPI) NOR flash memory; transmitting a read instruction to the SPI NOR flash memory; waiting for a read waiting time period, which is associated with a specification of the SPI NOR flash memory and a cycle of the first clock; waiting for a delay time period, which is associated with a delay setting value and a cycle of a second clock different from the first clock; receiving read data returned from the SPI NOR flash memory; and adjusting the delay time period according to whether the read data are correct or not. This invention improves the stability of read operation of the SPI NOR flash memory and has advantages of simple circuit and flexible adjustment.

Abstract: This invention discloses a memory control circuit and a method thereof. The memory control method includes the steps of: transmitting a first clock to a serial peripheral interface (SPI) NOR flash memory; transmitting a read instruction to the SPI NOR flash memory; waiting for a read waiting time period, which is associated with a specification of the SPI NOR flash memory and a cycle of the first clock; waiting for a delay time period, which is associated with a delay setting value and a cycle of a second clock different from the first clock; receiving read data returned from the SPI NOR flash memory; and adjusting the delay time period according to whether the read data are correct or not. This invention improves the stability of read operation of the SPI NOR flash memory and has advantages of simple circuit and flexible adjustment.

Abstract: A method for resetting a memory in the computer system includes turning on the computer system, and a memory controller of the computer system executing a boot code to initialize the memory. After the memory controller executes the boot code, the memory controller updates a programmable initialization code according to the boot code to generate an updated programmable initialization code. After resetting the computer system, the memory controller executes the updated programmable initialization code to restore the memory back to a default state. After the memory is restored to the default state, the memory controller executes the boot code to initialize the memory again. After the memory is initialized, the memory controller controls the memory to perform a normal operation.

Abstract: A processor includes a plurality of storage modules and an arbiter, where the storage modules are arranged for storing a plurality of read/write commands, respectively, and the read/write commands are arranged to read/write a memory external to the processor; and the arbiter is coupled to the storage modules, and is arranged to receive the read/write commands from the storage modules, and arrange a sequence of the read/write commands for transmitting to a memory controller.

Abstract: A memory controller includes an address decoder and a protocol controller, where the address decoder is arranged for decoding a received signal to generate a plurality of command signals, where the plurality of signals are for accessing a plurality of banks of the memory and the protocol controller is arranged for re-scheduling an executing order of the plurality of command signals according to opening banks and pages, and for accessing the memory according to the plurality of command signals.

Abstract: A processor includes a plurality of storage modules and an arbiter, where the storage modules are arranged for storing a plurality of read/write commands, respectively, and the read/write commands are arranged to read/write a memory external to the processor; and the arbiter is coupled to the storage modules, and is arranged to receive the read/write commands from the storage modules, and arrange a sequence of the read/write commands for transmitting to a memory controller.