Patents by Inventor Ya-Sheng Liu

Ya-Sheng Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Laterally diffused metal oxide semiconductor transistors
    Patent number: 8581344
    Abstract: A laterally diffused metal oxide semiconductor transistor. The laterally diffused metal oxide semiconductor transistor includes a substrate, a drain formed thereon, a source formed on the substrate, comprising a plurality of individual sub-sources respectively corresponding to various sides of the drain, a plurality of channels formed in the substrate between the sub-sources and the drain, a gate overlying a portion of the sub-sources and the channels, and a drift layer formed in the substrate underneath the drain.
    Type: Grant
    Filed: April 6, 2007
    Date of Patent: November 12, 2013
    Assignee: Vanguard International Semiconductor Corporation
    Inventor: Ya-Sheng Liu
  • Semiconductor device and fabrication method thereof
    Patent number: 8063439
    Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate which comprise a first type well and a second type well, and a plurality of junction regions therebetween, wherein each of the junction regions adjoins the first and the second type wells. A gate electrode disposed on the semiconductor substrate and overlies at least two of the junction regions. A source and a drain are in the semiconductor substrate oppositely adjacent to the gate electrode.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: November 22, 2011
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chih-Ping Lin, Pi-Kuang Chuang, Hung-Li Chang, Shih-Ming Chen, Hsiao-Ying Yang, Ya-Sheng Liu
  • SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF
    Publication number: 20110062500
    Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate which comprise a first type well and a second type well, and a plurality of junction regions therebetween, wherein each of the junction regions adjoins the first and the second type wells. A gate electrode disposed on the semiconductor substrate and overlies at least two of the junction regions. A source and a drain are in the semiconductor substrate oppositely adjacent to the gate electrode.
    Type: Application
    Filed: November 23, 2010
    Publication date: March 17, 2011
    Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Chih-Ping Lin, Pi-Kuang Chuang, Hung-Li Chang, Shih-Ming Chen, Hsiao-Ying Yang, Ya-Sheng Liu
  • Semiconductor device and fabrication method thereof
    Patent number: 7863147
    Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate which comprise a first type well and a second type well, and a plurality of junction regions therebetween, wherein each of the junction regions adjoins the first and the second type wells. A gate electrode disposed on the semiconductor substrate and overlies at least two of the junction regions. A source and a drain are in the semiconductor substrate oppositely adjacent to the gate electrode.
    Type: Grant
    Filed: July 22, 2008
    Date of Patent: January 4, 2011
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chih-Ping Lin, Pi-Kuang Chuang, Hung-Li Chang, Shih-Ming Chen, Hsiao-Ying Yang, Ya-Sheng Liu
  • Semiconductor structure
    Patent number: 7655978
    Abstract: A semiconductor structure including a substrate, a first well, a second well, a third well, a first doped region, and a second doped region. The substrate includes a first conductive type. The first well includes a second conductive type and is formed in the substrate. The second well includes the second conductive type and is formed in the first well. The third well includes the first conductive type, is formed in the substrate, and neighbors the first well. The first doped region includes the first conductive type and is formed in the first well. The second doped region includes the first conductive type and is formed in the first well. The first well surrounds all surfaces of the first and the second doped regions.
    Type: Grant
    Filed: November 27, 2007
    Date of Patent: February 2, 2010
    Assignee: Vanguard International Semiconductor Corporation
    Inventor: Ya-Sheng Liu
  • SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF
    Publication number: 20090236665
    Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate which comprise a first type well and a second type well, and a plurality of junction regions therebetween, wherein each of the junction regions adjoins the first and the second type wells. A gate electrode disposed on the semiconductor substrate and overlies at least two of the junction regions. A source and a drain are in the semiconductor substrate oppositely adjacent to the gate electrode.
    Type: Application
    Filed: July 22, 2008
    Publication date: September 24, 2009
    Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR
    Inventors: Chih-Ping Lin, Pi-Kuang Chuang, Hung-Li Chang, Shih-Ming Chen, Hsiao-Ying Yang, Ya-Sheng Liu
  • SEMICONDUCTOR STRUCTURE
    Publication number: 20090134478
    Abstract: A semiconductor structure including a substrate, a first well, a second well, a third well, a first doped region, and a second doped region. The substrate includes a first conductive type. The first well includes a second conductive type and is formed in the substrate. The second well includes the second conductive type and is formed in the first well. The third well includes the first conductive type, is formed in the substrate, and neighbors the first well. The first doped region includes the first conductive type and is formed in the first well. The second doped region includes the first conductive type and is formed in the first well. The first well surrounds all surfaces of the first and the second doped regions.
    Type: Application
    Filed: November 27, 2007
    Publication date: May 28, 2009
    Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventor: Ya-Sheng Liu