Patents by Inventor Yaakov Seidenwar

Yaakov Seidenwar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8970283
    Abstract: There is disclosed a switching arrangement comprising a switch with a plurality of individually controllable elementary switches connected in parallel between a first supply rail and a second supply rail. Each of the elementary switches can be in either one of a closed state and an open state independently of the others. A controller is adapted to dynamically control the closing or opening of the elementary switches, depending on the intensity of a current flowing through the switch. The number of elementary switches in the closed state is variable. The higher is the intensity of the current, the higher the number of elementary switches in the closed state. Thus, the impedance of the switch decreases when the current increases, and vice versa, and the voltage drop across the switch may be kept substantially constant.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: March 3, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Michael Priel, Anton Rozen, Yaakov Seidenwar
  • Patent number: 8832629
    Abstract: A method is provided for optimising cell variant selection within a design process for an integrated circuit device. The method comprises performing cell placement and signal routing for an integrated circuit being designed using default cell layout information for cell variants of at least one cell type. The method further comprises performing cell variant optimization comprising identifying at least one cell of the at least one cell type to be substituted and substituting a default cell variant of the at least one identified cell with an alternative variant of the at least one identified cell. The method further comprises, during cell optimization, configuring a pin interconnect modification for mapping at least one pin location of the alternative variant of the at least one identified cell to at least one pin contact for the default cell layout.
    Type: Grant
    Filed: July 23, 2010
    Date of Patent: September 9, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Anton Rozen, Michael Priel, Yaakov Seidenwar
  • Publication number: 20130249616
    Abstract: There is disclosed a switching arrangement comprising a switch with a plurality of individually controllable elementary switches connected in parallel between a first supply rail and a second supply rail. Each of the elementary switches can be in either one of a closed state and an open state independently of the others. A controller is adapted to dynamically control the closing or opening of the elementary switches, depending on the intensity of a current flowing through the switch. The number of elementary switches in the closed state is variable. The higher is the intensity of the current, the higher the number of elementary switches in the closed state. Thus, the impedance of the switch decreases when the current increases, and vice versa, and the voltage drop across the switch may be kept substantially constant.
    Type: Application
    Filed: December 17, 2010
    Publication date: September 26, 2013
    Applicant: FREESCALE SEMICONDUCTOR INC
    Inventors: Michael Priel, Anton Rozen, Yaakov Seidenwar
  • Publication number: 20130125077
    Abstract: A method is provided for optimising cell variant selection within a design process for an integrated circuit device. The method comprises performing cell placement and signal routing for an integrated circuit being designed using default cell layout information for cell variants of at least one cell type. The method further comprises performing cell variant optimisation comprising identifying at least one cell of the at least one cell type to be substituted and substituting a default cell variant of the at least one identified cell with an alternative variant of the at least one identified cell. The method further comprises, during cell optimisation, configuring a pin interconnect modification for mapping at least one pin location of the alternative variant of the at least one identified cell to at least one pin contact for the default cell layout.
    Type: Application
    Filed: July 23, 2010
    Publication date: May 16, 2013
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Anton Rozen, Michael Priel, Yaakov Seidenwar
  • Patent number: 8390369
    Abstract: A method and an electronic circuit, the electronic circuit includes: a module that comprises multiple flip-flops and a control signal providing circuit; a power management circuit arranged to provide to the module a supply voltage of a functional level when the module is in a functional mode, and to provide to the module a supply voltage of an idle level when the module is in an idle mode; wherein the control signal providing circuit is arranged to provide to the multiple flip-flops, when the module is in the functional mode, a control signal that facilitates a state change of each of the multiple flip-flops; wherein the control signal providing circuit is arranged to provide to the multiple flip-flops, when the module is in the idle mode, a control signal that prevents a state change of each of the multiple flip-flops; wherein the each of the control signal providing circuit and a plurality of flip-flops of the multiple flip-flops comprises at least one hybrid circuit that comprises a low-threshold transisto
    Type: Grant
    Filed: August 5, 2010
    Date of Patent: March 5, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Michael Priel, Anton Rozen, Yaakov Seidenwar
  • Publication number: 20120032719
    Abstract: A method and an electronic circuit, the electronic circuit includes: a module that comprises multiple flip-flops and a control signal providing circuit; a power management circuit arranged to provide to the module a supply voltage of a functional level when the module is in a functional mode, and to provide to the module a supply voltage of an idle level when the module is in an idle mode; wherein the control signal providing circuit is arranged to provide to the multiple flip-flops, when the module is in the functional mode, a control signal that facilitates a state change of each of the multiple flip-flops; wherein the control signal providing circuit is arranged to provide to the multiple flip-flops, when the module is in the idle mode, a control signal that prevents a state change of each of the multiple flip-flops; wherein the each of the control signal providing circuit and a plurality of flip-flops of the multiple flip-flops comprises at least one hybrid circuit that comprises a low-threshold transisto
    Type: Application
    Filed: August 5, 2010
    Publication date: February 9, 2012
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Michael Priel, Anton Rozen, Yaakov Seidenwar