Patents by Inventor Yadong SHAN

Yadong SHAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11984453
    Abstract: An array substrate includes: a first substrate (10), including a plurality of sub-pixel regions (101) arranged in an array along a row direction (X) and a column direction (Y); a pixel circuit layer, including a plurality of sub-pixel circuits; a planarization layer (17), provided with a first via hole (170) located in the sub-pixel regions (101), and includes at least one pattern portion (171), the pattern portion (171) includes a plurality of pattern units (171a) arranged in an array along the row direction (X) and the column direction (Y); and a reflective electrode layer, wherein the reflective electrode layer includes a plurality of reflective electrodes (18) that are mutually disconnected, each of the reflective electrodes (18) is located in one of the sub-pixel regions (101) and is electrically connected to the sub-pixel circuit through the first via hole (170).
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: May 14, 2024
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jiguo Wang, Jian Sun, Zhao Zhang, Liang Tian, Weida Qin, Zhen Wang, Han Zhang, Wenwen Qin, Xiaoyan Yang, Yue Shan, Wei Yan, Jian Zhang, Deshuai Wang, Yadong Zhang, Jiantao Liu
  • Patent number: 11961442
    Abstract: A shift register unit, a driving method, a drive circuit, and a display apparatus are disclosed. The shift register unit includes: a control circuit, which is configured to adjust signals of a first node and a second node according to an input signal end, a first control signal end, a second control signal end and a first reference signal end; a cascade circuit, which is configured to provide, according to the signal of the first node, a signal of a first cascade clock signal end to a cascade output end; and an output circuit, which is configured to provide, according to the signal of the first node, a signal of a control clock signal end to a drive output end, and provide, according to the signal of the second node, a signal of a second reference signal end to the drive output end.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: April 16, 2024
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Wei Yan, Wenwen Qin, Yue Shan, Deshuai Wang, Jiguo Wang, Zhen Wang, Xiaoyan Yang, Han Zhang, Jian Zhang, Yadong Zhang, Jian Sun
  • Patent number: 9741837
    Abstract: A bidirectional IGBT device, including a cellular structure including: two MOS structures, a substrate drift layer, two highly doped buried layers operating for carrier storage or field stop, two metal electrodes, and isolating dielectrics. Each MOS structure includes: a body region, a heavily doped source region, a body contact region, and a gate structure. Each gate structure includes: a gate dielectric and a gate conductive material. The two MOS structures are symmetrically disposed on the top surface and the back surface of the substrate drift layer. The heavily doped source region and the body contact region are disposed in the body region and independent from each other, and both surfaces of the heavily doped source region and the body contact region are connected to each of the two metal electrodes. The gate dielectric separates the gate conductive material from a channel region of each of the MOS structures.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: August 22, 2017
    Assignees: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA, INSTITUTE OF ELECTRONIC AND INFORMATION ENGINEERING IN DONGGUAN, UESTC
    Inventors: Jinping Zhang, Yadong Shan, Gaochao Xu, Xin Yao, Jingxiu Liu, Zehong Li, Min Ren, Bo Zhang
  • Publication number: 20160322483
    Abstract: A bidirectional IGBT device, including a cellular structure including: two MOS structures, a substrate drift layer, two highly doped buried layers operating for carrier storage or field stop, two metal electrodes, and isolating dielectrics. Each MOS structure includes: a body region, a heavily doped source region, a body contact region, and a gate structure. Each gate structure includes: a gate dielectric and a gate conductive material. The two MOS structures are symmetrically disposed on the top surface and the back surface of the substrate drift layer. The heavily doped source region and the body contact region are disposed in the body region and independent from each other, and both surfaces of the heavily doped source region and the body contact region are connected to each of the two metal electrodes. The gate dielectric separates the gate conductive material from a channel region of each of the MOS structures.
    Type: Application
    Filed: July 13, 2016
    Publication date: November 3, 2016
    Inventors: Jinping ZHANG, Yadong SHAN, Gaochao XU, Xin YAO, Jingxiu LIU, Zehong LI, Min REN, Bo ZHANG