Patents by Inventor Yahel DAVID
Yahel DAVID has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240036105Abstract: A semiconductor integrated circuit (IC) comprising a signal path combiner, comprising a plurality of input paths and an output path. The IC comprises a delay circuit having an input electrically connected to the output path, the delay circuit delaying an input signal by a variable delay time to output a delayed signal path. The IC may comprise a first storage circuit electrically connected to the output path and a second storage circuit electrically connected to the delayed signal path. The IC comprises a comparison circuit that compares outputs of the signal path combiner and the delayed signal, wherein the comparison circuit comprises a comparison output provided in a comparison data signal to at least one mitigation circuit.Type: ApplicationFiled: October 5, 2023Publication date: February 1, 2024Inventors: Evelyn LANDMAN, Shai COHEN, Yahel DAVID, Eyal FAYNEH, Inbar WEINTROB
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Publication number: 20240003968Abstract: A computerized method for IC classification, outlier detection and/or anomaly detection comprising using at least one hardware processor for testing each of the plurality of ICs in accordance with an IC design on a wafer, wherein the IC design comprises a plurality of sensors. The at least one hardware processor is used for testing each of the plurality of ICs by: collecting a plurality of sensor values, the plurality of sensor values including sensor values from each of the plurality of sensors; comparing the plurality of sensor values to a classification scheme, thereby obtaining a classification for each tested IC; and recording the classification of the tested IC.Type: ApplicationFiled: September 17, 2023Publication date: January 4, 2024Inventors: Evelyn LANDMAN, Yahel DAVID, Eyal FAYNEH, Shai COHEN, Yair TALKER
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Patent number: 11841395Abstract: A semiconductor integrated circuit (IC) comprising a signal path combiner, comprising a plurality of input paths and an output path. The IC comprises a delay circuit having an input electrically connected to the output path, the delay circuit delaying an input signal by a variable delay time to output a delayed signal path. The IC may comprise a first storage circuit electrically connected to the output path and a second storage circuit electrically connected to the delayed signal path. The IC comprises a comparison circuit that compares outputs of the signal path combiner and the delayed signal, wherein the comparison circuit comprises a comparison output provided in a comparison data signal to at least one mitigation circuit.Type: GrantFiled: July 11, 2022Date of Patent: December 12, 2023Assignee: PROTEANTECS LTD.Inventors: Evelyn Landman, Shai Cohen, Yahel David, Eyal Fayneh, Inbar Weintrob
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Publication number: 20230341460Abstract: An integrated circuit (IC) comprising: a margin measurement circuit configured to monitor multiple data paths of the IC and to output, at different times, different ranges of remaining margins of the multiple data paths; a workload sensor configured to output a value representing aggregate operational stress experienced by the IC over a period of time ending at each of the different times; and a processor configured to: (i) compute, based on the value output by said workload sensor, an upper bound and a lower bound of change of the remaining margin of the IC, and (ii) compute upper and lower bounds of a current remaining margin of the IC, based on (a) the upper and lower bounds of change, and (b) a remaining margin indicated by a border between two adjacent ranges outputted by the margin measurement circuit.Type: ApplicationFiled: June 29, 2023Publication date: October 26, 2023Inventors: Eyal FAYNEH, Inbar WEINTROB, Evelyn LANDMAN, Yahel DAVID, Shai COHEN, Guy REDLER
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Patent number: 11762013Abstract: A computerized method for IC classification, outlier detection and/or anomaly detection comprising using at least one hardware processor for testing each of the plurality of ICs in accordance with an IC design on a wafer, wherein the IC design comprises a plurality of sensors. The at least one hardware processor is used for testing each of the plurality of ICs by: collecting a plurality of sensor values, the plurality of sensor values including sensor values from each of the plurality of sensors; comparing the plurality of sensor values to a classification scheme, thereby obtaining a classification for each tested IC; and recording the classification of the tested IC.Type: GrantFiled: April 16, 2019Date of Patent: September 19, 2023Assignee: PROTEANTECS LTD.Inventors: Evelyn Landman, Yahel David, Eyal Fayneh, Shai Cohen, Yair Talker
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Patent number: 11740281Abstract: An integrated circuit (IC) comprising: a margin measurement circuit configured to monitor multiple data paths of the IC and to output, at different times, different ranges of remaining margins of the multiple data paths; a workload sensor configured to output a value representing aggregate operational stress experienced by the IC over a period of time ending at each of the different times; and a processor configured to: (i) compute, based on the value output by said workload sensor, an upper bound and a lower bound of change of the remaining margin of the IC, and (ii) compute upper and lower bounds of a current remaining margin of the IC, based on (a) the upper and lower bounds of change, and (b) a remaining margin indicated by a border between two adjacent ranges outputted by the margin measurement circuit.Type: GrantFiled: March 24, 2022Date of Patent: August 29, 2023Assignee: PROTEANTECS LTD.Inventors: Eyal Fayneh, Edi Shmueli, Alexander Burlak, Evelyn Landman, Inbar Weintrob, Yahel David, Shai Cohen, Guy Redler
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Publication number: 20230046999Abstract: A semiconductor integrated circuit (IC) comprising a signal path combiner, comprising a plurality of input paths and an output path. The IC comprises a delay circuit having an input electrically connected to the output path, the delay circuit delaying an input signal by a variable delay time to output a delayed signal path. The IC may comprise a first storage circuit electrically connected to the output path and a second storage circuit electrically connected to the delayed signal path. The IC comprises a comparison circuit that compares outputs of the signal path combiner and the delayed signal, wherein the comparison circuit comprises a comparison output provided in a comparison data signal to at least one mitigation circuit.Type: ApplicationFiled: July 11, 2022Publication date: February 16, 2023Inventors: Evelyn LANDMAN, Shai COHEN, Yahel DAVID, Eyal FAYNEH, Inbar WEINTROB
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Publication number: 20220349935Abstract: A semiconductor integrated circuit (IC) comprising a time-to-digital converter (TDC) configured to measure an input-to-output delay of an I/O buffer of a pad the IC, the measured delay reflecting a connection impedance of the pad. A circuit in the IC, or a computer in communication with the IC, determines electrical connection integrity of the pad based on the measured delay of the I/O buffer.Type: ApplicationFiled: July 18, 2022Publication date: November 3, 2022Inventors: Eyal FAYNEH, Shai COHEN, Evelyn LANDMAN, Yahel DAVID, Inbar WEINTROB
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Publication number: 20220343048Abstract: Determining one or more device parameters (Dp) of one or more parts of an integrated circuit (IC), including: simulating the IC; measuring one or more electrical characteristics of the one or more parts of the IC; using the one or more measured electrical characteristics of the one or more parts of the IC and the simulation to determine the one or more device parameters (Dp) of the one or more parts of the IC; for each part of the IC, determining a corresponding joint probability distribution of the one or more device parameters using the simulation; using maximum likelihood (ML) techniques to determine an estimate of the one or more device parameters; and using the one or more measured electrical characteristics of the one or more parts of the IC and the simulation to improve the estimate of the one or more device parameters.Type: ApplicationFiled: May 13, 2020Publication date: October 27, 2022Inventors: Eyal FAYNEH, Guy REDLER, Yahel DAVID, Inbar WEINTROB, Evelyn LANDMAN
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Publication number: 20220268644Abstract: A semiconductor integrated circuit (IC) comprising: a first ring oscillator (ROSC) circuit and a second ROSC circuit at spaced apart locations in the IC, each ROSC circuit having a respective oscillation frequency in operation that varies with temperature; a semiconductor temperature sensor, located in the IC proximate to the first ROSC circuit and providing a sensor output signal indicative of temperature; and at least one processor, configured to indicate a temperature at the second ROSC circuit based at least on: the sensor output signal, the oscillation frequency of the second ROSC circuit, and the oscillation frequency of the first ROSC circuit.Type: ApplicationFiled: July 29, 2020Publication date: August 25, 2022Inventors: Eyal FAYNEH, Guy REDLER, Evelyn LANDMAN, Inbar WEINTROB, Yahel DAVID, Faten TANASRA
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Publication number: 20220260630Abstract: An integrated circuit (IC) comprising: a margin measurement circuit configured to monitor multiple data paths of the IC and to output, at different times, different ranges of remaining margins of the multiple data paths; a workload sensor configured to output a value representing aggregate operational stress experienced by the IC over a period of time ending at each of the different times; and a processor configured to: (i) compute, based on the value output by said workload sensor, an upper bound and a lower bound of change of the remaining margin of the IC, and (ii) compute upper and lower bounds of a current remaining margin of the IC, based on (a) the upper and lower bounds of change, and (b) a remaining margin indicated by a border between two adjacent ranges outputted by the margin measurement circuit.Type: ApplicationFiled: March 24, 2022Publication date: August 18, 2022Inventors: Eyal FAYNEH, Edi SHMUELI, Alexander BURLAK, Evelyn LANDMAN, Inbar WEINTROB, Yahel DAVID, Shai COHEN, Guy REDLER
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Patent number: 11408932Abstract: Determination of one or more operating conditions (leakage current, temperature and/or workload) of a functional transistor in a semiconductor integrated circuit (IC). The functional transistor provides an electrical current, which is provided as an input to a ring oscillator (ROSC). The ROSC is located in the IC proximate to the functional transistor and has an oscillation frequency in operation. The one or more operating conditions of the functional transistor are determined based on the oscillation frequency of the ROSC.Type: GrantFiled: January 8, 2019Date of Patent: August 9, 2022Assignee: PROTEANTECS LTD.Inventors: Eyal Fayneh, Inbar Weintrob, Evelyn Landman, Yahel David, Shai Cohen, Guy Redler
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Patent number: 11391771Abstract: A semiconductor integrated circuit (IC) comprising a time-to-digital converter circuit (TDC), wherein time inputs to the TDC are (i) one or more input to an input/output (I/O) buffer of a pad of the IC, and (ii) one or more output from the I/O buffer. The IC comprises a digital comparator circuit electrically configured to: receive a stream of digital output values from the TDC, compare each value of the stream to one or more previous value in the stream, and when the comparison reflects a difference value greater than a threshold, issuing a notification to a user of the IC.Type: GrantFiled: November 22, 2018Date of Patent: July 19, 2022Assignee: PROTEANTECS LTD.Inventors: Eyal Fayneh, Shai Cohen, Evelyn Landman, Yahel David, Inbar Weintrob
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Patent number: 11385282Abstract: A semiconductor integrated circuit (IC) comprising a signal path combiner, comprising a plurality of input paths and an output path. The IC comprises a delay circuit having an input electrically connected to the output path, the delay circuit delaying an input signal by a variable delay time to output a delayed signal path. The IC may comprise a first storage circuit electrically connected to the output path and a second storage circuit electrically connected to the delayed signal path. The IC comprises a comparison circuit that compares outputs of the signal path combiner and the delayed signal, wherein the comparison circuit comprises a comparison output provided in a comparison data signal to at least one mitigation circuit.Type: GrantFiled: November 15, 2018Date of Patent: July 12, 2022Assignee: PROTEANTECS LTD.Inventors: Evelyn Landman, Shai Cohen, Yahel David, Eyal Fayneh, Inbar Weintrob
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Publication number: 20220012395Abstract: A method comprising using at least one hardware processor for: running a Monte Carlo simulation of possible integrated circuit (IC) process variations of each of a plurality of IC cell types, wherein each of the plurality of IC cell types is defined by multiple specific transistors and multiple specific interconnects; based on the results of the Monte Carlo simulation, creating a library of IC cell types and their corresponding behavioral values for each of the possible IC process variations, and storing the library in a non-transient memory; receiving an IC design embodied as a digital file; correlating the received IC design with the library; and predicting a frequency distribution and a power distribution of ICs manufactured according to the IC design.Type: ApplicationFiled: September 24, 2021Publication date: January 13, 2022Inventors: Evelyn LANDMAN, Yair TALKER, Eyal FAYNEH, Yahel DAVID, Shai COHEN, Inbar WEINTROB
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Patent number: 11132485Abstract: A method comprising using at least one hardware processor for: running a Monte Carlo simulation of possible integrated circuit (IC) process variations of each of a plurality of IC cell types, wherein each of the plurality of IC cell types is defined by multiple specific transistors and multiple specific interconnects; based on the results of the Monte Carlo simulation, creating a library of IC cell types and their corresponding behavioral values for each of the possible IC process variations, and storing the library in a non-transient memory; receiving an IC design embodied as a digital file; correlating the received IC design with the library; and predicting a frequency distribution and a power distribution of ICs manufactured according to the IC design.Type: GrantFiled: June 19, 2019Date of Patent: September 28, 2021Assignee: PROTEANTECS LTD.Inventors: Evelyn Landman, Yair Talker, Eyal Fayneh, Yahel David, Shai Cohen, Inbar Weintrob
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Publication number: 20210173007Abstract: A computerized method for IC classification, outlier detection and/or anomaly detection comprising using at least one hardware processor for testing each of the plurality of ICs in accordance with an IC design on a wafer, wherein the IC design comprises a plurality of sensors. The at least one hardware processor is used for testing each of the plurality of ICs by: collecting a plurality of sensor values, the plurality of sensor values including sensor values from each of the plurality of sensors; comparing the plurality of sensor values to a classification scheme, thereby obtaining a classification for each tested IC; and recording the classification of the tested IC.Type: ApplicationFiled: April 16, 2019Publication date: June 10, 2021Inventors: Evelyn LANDMAN, Yahel DAVID, Eyal FAYNEH, Shai COHEN, Yair TALKER
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Publication number: 20210165941Abstract: A method comprising using at least one hardware processor for: running a Monte Carlo simulation of possible integrated circuit (IC) process variations of each of a plurality of IC cell types, wherein each of the plurality of IC cell types is defined by multiple specific transistors and multiple specific interconnects; based on the results of the Monte Carlo simulation, creating a library of IC cell types and their corresponding behavioral values for each of the possible IC process variations, and storing the library in a non-transient memory; receiving an IC design embodied as a digital file; correlating the received IC design with the library; and predicting a frequency distribution and a power distribution of ICs manufactured according to the IC design.Type: ApplicationFiled: June 19, 2019Publication date: June 3, 2021Inventors: Evelyn LANDMAN, Yair TALKER, Eyal FAYNEH, Yahel DAVID, Shai COHEN, Inbar WEINTROB
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Publication number: 20200393506Abstract: A semiconductor integrated circuit (IC) comprising a signal path combiner, comprising a plurality of input paths and an output path. The IC comprises a delay circuit having an input electrically connected to the output path, the delay circuit delaying an input signal by a variable delay time to output a delayed signal path. The IC may comprise a first storage circuit electrically connected to the output path and a second storage circuit electrically connected to the delayed signal path. The IC comprises a comparison circuit that compares outputs of the signal path combiner and the delayed signal, wherein the comparison circuit comprises a comparison output provided in a comparison data signal to at least one mitigation circuit.Type: ApplicationFiled: November 15, 2018Publication date: December 17, 2020Inventors: Evelyn LANDMAN, Shai COHEN, Yahel DAVID, Eyal FAYNEH, Inbar WEINTROB
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Publication number: 20200363468Abstract: A semiconductor integrated circuit (IC) comprising a time-to-digital converter circuit (TDC), wherein time inputs to the TDC are (i) one or more input to an input/output (I/O) buffer of a pad of the IC, and (ii) one or more output from the I/O buffer. The IC comprises a digital comparator circuit electrically configured to: receive a stream of digital output values from the TDC, compare each value of the stream to one or more previous value in the stream, and when the comparison reflects a difference value greater than a threshold, issuing a notification to a user of the IC.Type: ApplicationFiled: November 22, 2018Publication date: November 19, 2020Inventors: Eyal FAYNEH, Shai COHEN, Evelyn LANDMAN, Yahel DAVID, Inbar WEINTROB