Abstract: An MPS generation method, the method constituted of: at a predetermined frequency, alternately outputting a first MPS current pulse for a predetermined first time period and not outputting the first MPS current pulse for a predetermined first off time period; during the first time period, determining the magnitude of a current drawn by an input capacitor of a DC to DC converter; and responsive to the determined input capacitor current magnitude, outputting between the first terminal and the second terminal a second MPS current pulse for a predetermined second time period during the predetermined first off time period.

Abstract: An MPS generation method, the method constituted of: at a predetermined frequency, alternately outputting a first MPS current pulse for a predetermined first time period and not outputting the first MPS current pulse for a predetermined first off time period; during the first time period, determining the magnitude of a current drawn by an input capacitor of a DC to DC converter; and responsive to the determined input capacitor current magnitude, outputting between the first terminal and the second terminal a second MPS current pulse for a predetermined second time period during the predetermined first off time period.

Abstract: A PoE power utilization method constituted of: detecting a first function of a voltage between a current path node and a current return path node during a first time period and during a second time period, the second time period different than the first time period; sensing a second function of the magnitude of a current flowing through the current path during the second time period; responsive to the detected first time period voltage function, the detected second time period voltage function and the sensed second time period current magnitude function, determining a third function of a resistance seen by the current path; and outputting an indication of the determined resistance function.

Abstract: A power over Ethernet (PoE) connection check method comprising: for a first time period, generating a first detection power over the first set of wires while not generating a second detection power over the second set of wires and obtaining a first indication of a power attribute over the first set of wires; during a second time period, generating the first detection power and generating a second detection power, greater than the first detection power, over the first set of wires; during the second time period, obtaining a second indication of the power attribute over the first set of wires; determining a first difference between the first indication and the second indication; and controlling a first power enable circuit and a second power enable circuit to provide power to the powered device over the first and second sets of wires respectively, responsive to the determined difference.

Abstract: An MPS generation method, the method constituted of: at a predetermined frequency, alternately outputting a first MPS current pulse for a predetermined first time period and not outputting the first MPS current pulse for a predetermined first off time period; during the first time period, determining the magnitude of a current drawn by an input capacitor of a DC to DC converter; and responsive to the determined input capacitor current magnitude, outputting between the first terminal and the second terminal a second MPS current pulse for a predetermined second time period during the predetermined first off time period.

Abstract: An integrated limiter and active filter constituted of: an input node; an output node; a transistor coupled between the input node and the output node; a first control circuit coupled to the control terminal of the transistor and arranged to limit the amount of current flowing through the output node to a predetermined value which is responsive to a signal received at a first reference input; a second control circuit coupled to the control terminal of the transistor and arranged to limit the voltage appearing at the output node to a predetermined value which is responsive to a signal received at a second reference input; and a third control circuit coupled to input node and arranged to provide the second reference input, the third control circuit arranged to set the second reference input responsive to the input voltage and to a predetermined maximum allowed output voltage.

Abstract: A PoE midspan injector constituted of: an Ethernet device side data port; a PD side data port; a plurality of pairs of data wires coupling the Ethernet device and PD side data ports; a power reception port; a pair of first type coils; and a pair of second type coils, each second type coil coupled in series to a respective first type coil thereby forming a coil set, wherein the power reception port is coupled to each wire of a pair of data wire pairs at a respective power node, via a respective coil set, wherein the impedance of the first type coil is greater than the impedance of the second type coil when data is being transmitted at a minimum frequency, and wherein the impedance of the second type coil is greater than the impedance of the first type coil when data is being transmitted at a maximum frequency.

Abstract: A PoE power utilization method constituted of: detecting a first function of a voltage between a current path node and a current return path node during a first time period and during a second time period, the second time period different than the first time period; sensing a second function of the magnitude of a current flowing through the current path during the second time period; responsive to the detected first time period voltage function, the detected second time period voltage function and the sensed second time period current magnitude function, determining a third function of a resistance seen by the current path; and outputting an indication of the determined resistance function.

Abstract: A power over Ethernet (PoE) connection check method comprising: for a first time period, generating a first detection power over the first set of wires while not generating a second detection power over the second set of wires and obtaining a first indication of a power attribute over the first set of wires; during a second time period, generating the first detection power and generating a second detection power, greater than the first detection power, over the first set of wires; during the second time period, obtaining a second indication of the power attribute over the first set of wires; determining a first difference between the first indication and the second indication; and controlling a first power enable circuit and a second power enable circuit to provide power to the powered device over the first and second sets of wires respectively, responsive to the determined difference.

Abstract: A midspan injector constituted of: a circuit board; a power injection circuit; a plurality of electrical paths without crossover; a first jack comprising a plurality of pins; and a second jack comprising a plurality of pins, each in communication with a respective pin of the first jack via a respective electrical path, wherein each of the first jack and the second jack exhibits a receptacle with a protrusion of the receptacle extending from a side thereof, wherein the receptacle protrusion of the first jack extends along a first vector and the receptacle protrusion of the second jack extends along a second vector, the direction of the second vector opposing the direction of the first vector, and wherein the power injection circuit is arranged to: receive common mode DC power from a power source; and inject the received power into the plurality of electrical paths.

Abstract: A PoE midspan injector constituted of: an Ethernet device side data port; a PD side data port; a plurality of pairs of data wires coupling the Ethernet device and PD side data ports; a power reception port; a pair of first type coils; and a pair of second type coils, each second type coil coupled in series to a respective first type coil thereby forming a coil set, wherein the power reception port is coupled to each wire of a pair of data wire pairs at a respective power node, via a respective coil set, wherein the impedance of the first type coil is greater than the impedance of the second type coil when data is being transmitted at a minimum frequency, and wherein the impedance of the second type coil is greater than the impedance of the first type coil when data is being transmitted at a maximum frequency.

Abstract: A power classification circuit is provided. The circuit includes a control circuit, a current sensor, and an indicator signal, and a voltage source. The control circuit is configured to control the voltage source to provide a first predetermined classification voltage, detect a first classification current, provide a predetermined indexing voltage, and control the at least one voltage source to provide a second predetermined classification voltage and detect a second classification current. The control circuit is configured to detect the first classification current within a classification current range, detect a draw down current outside of the classification current range, and detect the second classification current within the classification current range. The control circuit is further configured to set the indicator signal to a first predetermined state indicating a power type based on the detected first classification current, draw down current, and the second classification current.

Abstract: A power saving arrangement for use with a phase cut dimmer, the power saving arrangement constituted of: a power converter arranged to convert a received alternating current power signal to a direct current signal; a detector arranged to detect the presence, or absence, of the phase cut dimmer blocking a portion of an alternating current mains power sine wave from reaching the power converter; and a controllable minimum holding current circuit in communication with the received alternating current power signal, the controllable minimum holding current circuit responsive to an output of the detector, wherein in the event that the detector detects the absence of the phase cut dimmer, the controllable minimum holding current circuit is disabled such that a minimum holding current is not provided.

Abstract: An integrated limiter and active filter constituted of: an input node; an output node; a transistor coupled between the input node and the output node; a first control circuit coupled to the control terminal of the transistor and arranged to limit the amount of current flowing through the output node to a predetermined value which is responsive to a signal received at a first reference input; a second control circuit coupled to the control terminal of the transistor and arranged to limit the voltage appearing at the output node to a predetermined value which is responsive to a signal received at a second reference input; and a third control circuit coupled to input node and arranged to provide the second reference input, the third control circuit arranged to set the second reference input responsive to the input voltage and to a predetermined maximum allowed output voltage.

Abstract: A circuit is provided. The circuit includes a control circuit and a voltage sensor coupled to the control circuit. The control circuit, responsive to the voltage sensor, is configured to detect a first classification voltage within a classification voltage range defined by a lower classification voltage limit and upper classification voltage limit, detect, after detecting the first classification voltage, an indexing voltage outside of the classification voltage range, and detect, after detecting the indexing voltage, a second classification voltage within the classification voltage range. The control circuit is further configured to set an indicator signal to a first predetermined state indicating a power type based on the detected first classification voltage, indexing voltage and second classification voltage.

Abstract: A multiplexed sigma delta modulator constituted of: a control circuitry; a multiplexer responsive to the control circuitry and arranged to receive a plurality of input signals; a comparing circuit, a first input of the comparing circuit coupled to the output of the multiplexer; an integrator, the input of the integrator coupled to the output of the comparing circuit; a latched comparing circuit, one input of the latched comparing circuit coupled to the output of the integrator; a plurality of storage elements, each associated with one of the plurality of inputs; and a feedback circuit arranged to feedback the output of the latched comparing circuit to the second input of the comparing circuit, wherein the control circuitry is further arranged to store the charge of an element of the integrator on the associated storage element when the associated signal is not passed by the multiplexer to the output of the multiplexer.

Abstract: A circuit is provided. The circuit includes a control circuit, a voltage sensor coupled to the control circuit, an indicator signal coupled to the control circuit, and at least one current source. The control circuit, responsive to the voltage sensor, is configured to detect a first classification voltage within a classification voltage range defined by a lower classification voltage limit and upper classification voltage limit, detect, after detecting the first classification voltage, an indexing voltage outside of the classification voltage range, and detect a second classification voltage within the classification voltage range. The at least one current source provides a first and second predetermined classification current responsive to the first classification voltage and the second classification voltage, respectively.

Abstract: A circuit is provided. The circuit includes a control circuit, a voltage sensor coupled to the control circuit, and an indicator signal coupled to the control circuit. The control circuit, responsive to the voltage sensor, is configured to detect a first classification voltage within a classification voltage range defined by a lower classification voltage limit and upper classification voltage limit, detect, after detecting the first classification voltage, an indexing voltage outside of the classification voltage range, and detect, after detecting the indexing voltage, a second classification voltage within the classification voltage range. The control circuit is further configured to set the indicator signal to a first predetermined state indicating a power type based on the detected first classification voltage, indexing voltage and second classification voltage.

Abstract: A circuit is provided. The circuit includes a control circuit, a voltage sensor coupled to the control circuit, and an indicator signal coupled to the control circuit. The control circuit, responsive to the voltage sensor, is configured to detect a first classification voltage within a classification voltage range defined by a lower classification voltage limit and upper classification voltage limit, detect, after detecting the first classification voltage, an indexing voltage outside of the classification voltage range, and detect, after detecting the indexing voltage, a second classification voltage within the classification voltage range. The control circuit is further configured to set the indicator signal to a first predetermined state indicating a power type based on the detected first classification voltage, indexing voltage and second classification voltage.

Abstract: A solid state lighting controller arranged for use with a single stage power factor correction switched mode power supply, a light emitting diode (LED) string and a current sense element arranged to sense current through the LED string, the solid state lighting controller constituted of: a current governor in series with the LED string exhibiting a governor differential amplifier and a governor electronically controlled switch responsive to the output of the governor differential amplifier, the current governor arranged to limit current flow through the LED string responsive to a current limit reference; and a feedback circuit exhibiting an error amplifier, the feedback circuit arranged to feedback a signal to the power factor correction switched mode power supply controller whose value is a function of the difference between the current through the LED string sensed by the current sense element and a target current signal.