Abstract: A resistive memory structure comprises a resistive memory element, a resistance block electrically connected to the memory element through an electrical node, and an interpretation circuit electrically connected to the node and configured to interpret a voltage at the node and to indicate a resistive state of the memory element based on the voltage at the node. The interpretation circuit includes one or more active devices, one or more passive devices each electrically connected to a respective one of the active devices, and one or more comparators each electrically connected to a respective one of the active devices. Each of the active devices and the passive device electrically connected thereto are configured to provide a voltage level to the respective comparator to which the active device is connected. The comparator(s) are configured to indicate the resistive state of the memory element based on the provided voltage level(s).

Abstract: A resistive memory structure comprises at least one resistive memory element configured to store one or more bits of data and a circuit electrically connected to the resistive memory element for use in performing at least one of a read or write operation on the at least one resistive memory element. The circuit includes a resistor electrically connected in series to the resistive memory element thereby forming a voltage divider and electrical node therebetween, and an interpretation circuit electrically connected to the electrical node formed between the resistive memory element and the resistor. The interpretation circuit is configured to interpret a voltage at the electrical node and to determine a resistive state of the resistive memory element based on the voltage at the electrical node.

Abstract: A resistive memory structure comprises a resistive memory element, a resistance block electrically connected to the memory element through an electrical node, and an interpretation circuit electrically connected to the node and configured to interpret a voltage at the node and to indicate a resistive state of the memory element based on the voltage at the node. The interpretation circuit includes one or more active devices, one or more passive devices each electrically connected to a respective one of the active devices, and one or more comparators each electrically connected to a respective one of the active devices. Each of the active devices and the passive device electrically connected thereto are configured to provide a voltage level to the respective comparator to which the active device is connected. The comparator(s) are configured to indicate the resistive state of the memory element based on the provided voltage level(s).

Abstract: A resistive memory structure comprises at least one resistive memory element configured to store one or more bits of data and a circuit electrically connected to the resistive memory element for use in performing at least one of a read or write operation on the at least one resistive memory element. The circuit includes a resistor electrically connected in series to the resistive memory element thereby forming a voltage divider and electrical node therebetween, and an interpretation circuit electrically connected to the electrical node formed between the resistive memory element and the resistor. The interpretation circuit is configured to interpret a voltage at the electrical node and to determine a resistive state of the resistive memory element based on the voltage at the electrical node.