Abstract: The present application provides a structure and method for improving near-infrared quantum efficiency of a backside illuminated image sensor. The structure includes a substrate and a plurality of photodiodes. The photodiodes are formed in the substrate. A cell deep trench isolation structure is fabricated on a surface of each photodiode. The cross section of the cell deep trench isolation structure 3 parallel to the surface of said photodiode comprises one or both of a four-quadrant square shape and a Union Jack shape. In the present application, by fabricating the cell deep trench isolation structures on the surface of each photodiode, the cell deep trench isolation structures increase light scattering in the photodiode, thus the optical path is increased, thereby improving the absorption of incident light, especially in near-infrared wavelength. As a result the quantum efficiency and sensor's imaging quality are improved.

Abstract: The application discloses a method of applying the stress memorization technique in making the semiconductor device which includes: step 1: forming a front gate structure on a silicon wafer having front and back surfaces; step 2: forming sidewalls including a first silicon nitride sidewall, a first silicon nitride layer corresponding to the first silicon nitride sidewall covering a first polysilicon layer on the wafer's back surface; step 3: growing a second silicon nitride layer on the wafer's front surface; step 4: etching the silicon nitride after stress transfer is completed, including: step 41: performing front single-wafer wet etching; step 42: performing batch wet etching to completely remove the second silicon nitride layer and reduces the thickness of the first silicon nitride layer on the back surface; step 5: completing the subsequent process. The application can improve the wafer flatness for improved photolithography for back-end-of-line processes and thereby increasing product yield.

Abstract: The application discloses a method of applying the stress memorization technique in making the semiconductor device which includes: step 1: forming a front gate structure on a silicon wafer having front and back surfaces; step 2: forming sidewalls including a first silicon nitride sidewall, a first silicon nitride layer corresponding to the first silicon nitride sidewall covering a first polysilicon layer on the wafer's back surface; step 3: growing a second silicon nitride layer on the wafer's front surface; step 4: etching the silicon nitride after stress transfer is completed, including: step 41: performing front single-wafer wet etching; step 42: performing batch wet etching to completely remove the second silicon nitride layer and reduces the thickness of the first silicon nitride layer on the back surface; step 5: completing the subsequent process. The application can improve the wafer flatness for improved photolithography for back-end-of-line processes and thereby increasing product yield.

Abstract: A method of manufacturing a semiconductor device is disclosed, which can completely remove hard mask residues left along boundaries between a high-voltage device region and STI structures after a dry etch process, by partially reducing a thickness of each of the exposed portion of the respective STI structures adjacent to the high-voltage device region so as to sufficiently expose the residues. As a result, after a portion of an underlying pad oxide corresponding to the high-voltage device region is removed in a subsequent process, the exposed surface of the substrate is uniform with a smooth and clear border. Therefore, no sharp corners will emerge at a border of a gate oxide subsequently grown on the exposed surface of the substrate, and the gate oxide is thus morphologically improved, thereby resulting in an improvement of the reliability of the high-voltage semiconductor device being fabricated.

Abstract: A method of manufacturing a semiconductor device is disclosed, which can completely remove hard mask residues left along boundaries between a high-voltage device region and STI structures after a dry etch process, by partially reducing a thickness of each of the exposed portion of the respective STI structures adjacent to the high-voltage device region so as to sufficiently expose the residues. As a result, after a portion of an Underlying pad oxide corresponding to the high-voltage device region is removed in a subsequent process, the exposed surface of the substrate is uniform with a smooth and clear border. Therefore, no sharp corners will emerge at a border of a gate oxide subsequently grown on the exposed surface of the substrate, and the gate oxide is thus morphologically improved, thereby resulting in an improvement of the reliability of the high-voltage semiconductor device being fabricated.