Abstract: The present invention provides a supporting hook structure, comprising a sleeve, a fixing rod, a first limit unit, a hook and a fixing device. The fixing rod is connected to the side surface of the sleeve. The hook body is connected to one end of the sleeve. The first limit unit is arranged on the side surface of the sleeve and adjacent to the hook body. The first limit unit makes the hook body rotates with the axis direction of the sleeve as a rotation axis. The fixing device is connected to the other end of the sleeve to fix the rotating position of the hook body. Through the above, the hook part enters the proximal thigh from a surgical entrance and the hook part rotates to make the hook part abut against the proximal femur to complete the positioning and fixation of the femur hook structure to the femur.

Abstract: An inspection system includes an excitation light source, a voltage-sensing film, an illumination light source, an image capture device. The excitation light source provides an excitation beam to light-emitting diodes to generate open-circuit voltages. The voltage-sensing film is at a top side of the light-emitting diodes and includes a voltage-sensing medium layer and a first electrode layer. The first electrode layer is in the voltage-sensing medium layer to provide a gain effect of the open-circuit voltages, so that the voltage-sensing medium layer senses the open-circuit voltages, and a display of the voltage-sensing medium layer is changed with a portion or all of the open-circuit voltages. The illumination light source provides an illumination beam to the voltage-sensing film to generate a sensing image according to a display change. The image capture device is on a transmission path of the sensing image and receives the sensing image to generate an inspection result.

Abstract: An acute kidney injury predicting system and a method thereof are proposed. A processor reads the data to be tested, the detection data, the machine learning algorithm and the risk probability comparison table from a main memory. The processor trains the detection data according to the machine learning algorithm to generate an acute kidney injury prediction model, and inputs the data to be tested into the acute kidney injury prediction model to generate an acute kidney injury characteristic risk probability and a data sequence table. The data sequence table lists the data to be tested in sequence according to a proportion of each of the data to be tested in the acute kidney injury characteristics. The processor selects one of the medical treatment data from the risk probability comparison table according to the acute kidney injury characteristic risk probability.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a gate strip, a source doped region and a body doped region. The substrate has an active region. The gate strip is disposed on the substrate within the active region. The gate strip extends along a first direction. The source doped region is located in the active region and adjacent to a first side of the gate strip along the first direction. The body doped region is located in the active region and adjacent to the first side of the gate strip. The body doped region and the source doped region have opposite conductivity types. The body doped region has a first length along a second direction that is different from the first direction, wherein the first length gradually changes along the first direction.

Abstract: The present invention provides a human CD16+ natural killer cell line and a CAR-expressing human CD16+ natural killer cell line. These human CD16+ natural killer cell line and a CAR-expressing human CD16+ natural killer cell line does not include synthetic, genetically modified or purposely deliberately delivered polynucleotide encoding the CD16 receptor and are non-tumorigenic cell lines. Therefore, this human CD16+ natural killer cell line and a CAR-expressing human CD16+ natural killer cell line might provide considerable long-term safety for disease treatment.

Abstract: The present invention provides a human CD16+ natural killer cell line. This human CD16+ natural killer cell line does not include synthetic, genetically modified or deliberately delivered polynucleotide encoding the CD16 receptor and is a non-tumorigenic cell line. Therefore, this human CD16+ natural killer cell line might provide considerable long-term safety for disease treatment.

Abstract: The present invention relates to a method for synthesizing tetrahydroisoquinoline thiazolidine, which can be conducted under a relatively mild reaction condition and can rapidly synthesize tetrahydroisoquinoline thiazolidine.

Abstract: The invention relates to a method for synthesizing tetrahydroisoquinoline oxazolidine. The method is carried out at a room temperature between 20° C. and 35° C.

Abstract: A cross flow fan flying device includes a first thrusting means having a first cross flow fan and a second thrusting means having a second cross flow fan, wherein the first flow fan and the second cross flow fan rotate in directions opposite with each other, and the cross flow fan flying device is driven and flies by airflow thrust generated by the first cross flow fan and the second cross flow fan.

Abstract: An LED (Light-Emitting Diode) light tube includes a transparent tube, a phosphor layer and a base board. The phosphor layer is coated on a surface of the transparent tube, wherein a thickness of the phosphor layer is 10-100 ?m. The base board is arranged inside the transparent tube for carrying a plurality of LEDs (Light-Emitting Diodes), wherein the length between the base board and the top of the transparent tube is H, and the distance between every two adjacent LEDs is P, and H/P is not smaller than 0.134 and H is 9.5-38 mm.

Abstract: A 2×VDD-tolerant input/output (I/O) buffer circuit with process, voltage, and temperature (PVT) compensation suitable for CMOS technology is disclosed. A 2×VDD-tolerant I/O buffer with a PVT compensation circuit is implemented with novel 2×VDD-tolerant logic gates. Output slew rate variations can be kept within smaller ranges to match maximum and minimum timing specifications. A 2×VDD tolerant logic circuit for implementing the I/O buffer is also disclosed.

Abstract: A 2×VDD-tolerant input/output (I/O) buffer circuit with process, voltage, and temperature (PVT) compensation suitable for CMOS technology is disclosed. A 2×VDD-tolerant I/O buffer with a PVT compensation circuit is implemented with novel 2×VDD-tolerant logic gates. Output slew rate variations can be kept within smaller ranges to match maximum and minimum timing specifications. A 2×VDD tolerant logic circuit for implementing the I/O buffer is also disclosed.

Abstract: The invention relates to an I/O buffer with twice the supply voltage tolerance using normal supply voltage devices. The I/O buffer of the invention includes a driver, a first level converter, a gate-controlled circuit and a dynamic source output stage. Signals of the I/O buffer are classified into a first voltage range and a second voltage range. The first voltage range is zero to the normal supply voltage, and the second voltage range is the normal supply voltage to twice the supply voltage. Therefore, the voltage between any two terminals of any of the transistors in the I/O buffer does not exceed the normal supply voltage so that the I/O buffer of the invention can transmit and receive signals with a voltage swing twice as high as the normal power supply voltage using normal supply voltage devices and without gate-oxide reliability problems.

Abstract: The invention relates to an I/O buffer with twice the supply voltage tolerance using normal supply voltage devices. The I/O buffer of the invention includes a driver, a first level converter, a gate-controlled circuit and a dynamic source output stage. Signals of the I/O buffer are classified into a first voltage range and a second voltage range. The first voltage range is zero to the normal supply voltage, and the second voltage range is the normal supply voltage to twice the supply voltage. Therefore, the voltage between any two terminals of any of the transistors in the I/O buffer does not exceed the normal supply voltage so that the I/O buffer of the invention can transmit and receive signals with a voltage swing twice as high as the normal power supply voltage using normal supply voltage devices and without gate-oxide reliability problems.