Abstract: This invention provides a vehicle powered by a surface-mediated cell (SMC)-based power source, comprising a vehicle frame, at least a wheel supporting the frame or a propeller connected to the frame, a drive unit connected to the wheel or propeller, and a power source electrically connected to the drive unit, wherein the power source contains at least a surface-mediated cell. The vehicle can be a micro-EV (using the SMC for the stop-start function), HEV, plug-in HEV, all-electric vehicle, power-assisted bicycle, scooter, motorcycle, tricycle, automobile, wheelchair, fork lift, golf cart, specialty vehicle, bus, truck, train, rapid-transit vehicle, boat, or air vehicle. The ultra-high power density enables the SMC to provide pulsed power or increased current demands when the vehicle is accelerating or hill-climbing. The SMC also enables the power source to recuperate the braking energy when the vehicle decelerates, brakes, or simply moves down-hill.

Abstract: The present invention provides a multi-component hybrid electrode for use in an electrochemical super-hybrid energy storage device. The hybrid electrode contains at least a current collector, at least an intercalation electrode active material storing lithium inside interior or bulk thereof, and at least an intercalation-free electrode active material having a specific surface area no less than 100 m2/g and storing lithium on a surface thereof, wherein the intercalation electrode active material and the intercalation-free electrode active material are in electronic contact with the current collector. The resulting super-hybrid cell exhibits exceptional high power and high energy density, and long-term cycling stability that cannot be achieved with conventional supercapacitors, lithium-ion capacitors, lithium-ion batteries, and lithium metal secondary batteries.

Abstract: An energy storage stack of at least two surface-mediated cells (SMCs) internally connected in parallel or in series. The stack includes: (A) At least two SMC cells, each consisting of (i) a cathode comprising a porous cathode current collector and a cathode active material; (ii) a porous anode current collector; and (iii) a porous separator disposed between the cathode and the anode; (B) A lithium-containing electrolyte in physical contact with all the electrodes, wherein the cathode active material has a specific surface area no less than 100 m2/g in direct physical contact with the electrolyte to receive lithium ions therefrom or to provide lithium ions thereto; and (C) A lithium source. This new-generation energy storage device exhibits the highest power densities of all energy storage devices, much higher than those of all the lithium ion batteries, lithium ion capacitors, and supercapacitors.

Abstract: The present invention provides a battery or supercapacitor current collector which is prelithiated. The prelithiated current collector comprises: (a) an electrically conductive substrate having two opposed primary surfaces, and (b) a mixture layer of carbon (and/or other stabilizing element, such as B, Al, Ga, In, C, Si, Ge, Sn, Pb, As, Sb, Bi, Te, or a combination thereof) and lithium or lithium alloy coated on at least one of the primary surfaces, wherein lithium element is present in an amount of 1% to 99% by weight of the mixture layer. This current collector serves as an effective and safe lithium source for a wide variety of electrochemical energy storage cells, including the rechargeable lithium cell (e.g. lithium-metal, lithium-ion, lithium-sulfur, lithium-air, lithium-graphene, lithium-carbon, and lithium-carbon nanotube cell) and the lithium ion based supercapacitor cell (e.g, symmetric ultracapacitor, asymmetric ultracapacitor, hybrid supercapacitor-battery, or lithium-ion capacitor).

Abstract: The present disclosure provides techniques for recovering source stream clock data at the sink in a high definition multimedia digital content transport system. The disclosure includes a fractional-N Phase-Locked Loop (PLL) based clock generator, a programmable Sigma-Delta Modulator (SDM), and a clock data calibrator to fully recover the original source stream clock data. The fractional-N PLL provides flexible source stream clock recovery. When there is a frequency deviation between the original clock and the regenerated clock, the clock data calibrator control circuit adjusts the clock data, preventing any stream data buffer overflow or underflow problems. The disclosed techniques are compatible with the sink devices based on the standards of DisplayPort and HDMI.

Abstract: A method of calibrating a PLL that includes forcing a control voltage input to a voltage controlled oscillator to be a reference voltage and setting a calibration divider coupled to receive an output clock signal from the voltage controlled oscillator such that the calibration divider utilizes one of a plurality of divisors that results in the output clock signal having a high frequency can substantially avoid overshoot and glitch problems associated with conventional PLL calibrations.

Abstract: A delay line circuit is provided. The delay line circuit includes a reference voltage generating circuit that generates a reference voltage, the reference voltage having a positive temperature coefficient. The delay line circuit also includes a voltage regulating circuit that generates a regulated voltage in response to the generated reference voltage as an input, and a delay chain circuit coupled to the voltage regulator to receive the regulated voltage, the delay chain circuit outputting a delay signal. In an embodiment consistent with the present invention, the reference voltage generating circuit includes a bandgap reference voltage circuit. In another embodiment consistent with the present invention, the reference voltage generating circuit includes a proportional to absolute temperature (PTAT) circuit.

Abstract: A method of calibrating a PLL that includes forcing a control voltage input to a voltage controlled oscillator to be a reference voltage and setting a calibration divider coupled to receive an output clock signal from the voltage controlled oscillator such that the calibration divider utilizes one of a plurality of divisors that results in the output clock signal having a high frequency can substantially avoid overshoot and glitch problems associated with conventional PLL calibrations.

Abstract: The methods and systems presented herein provide an improved means of correcting the variation of Voltage Output Differential (VOD) in differential drivers. In some embodiments, a high-precision reference voltage is generated not only based on a desired VOD, but also by monitoring the Voltage Common Mode (VCM) in a differential driver. In some embodiments, the VOD is then compared with the high-precision reference voltage to correct the output current. The result is a low-variation output voltage.

Abstract: The methods and systems presented herein provide an improved means of correcting the variation of Voltage Output Differential (VOD) in differential drivers. In some embodiments, a high-precision reference voltage is generated not only based on a desired VOD, but also by monitoring the Voltage Common Mode (VCM) in a differential driver. In some embodiments, the VOD is then compared with the high-precision reference voltage to correct the output current. The result is a low-variation output voltage.