Abstract: A video processing circuit includes a video generating unit for generating a video output stream, a data generating unit (e.g. graphic generating unit) for providing a data stream (e.g. graphical stream), and a communication interface circuit. The communication interface circuit has a mode provided for merging the video output stream and the graphical stream to transmit a first merged signal through a channel. In the mode, the communication interface circuit merges the video output stream and the data stream by increasing a working frequency of the communication interface circuit to increase bandwidths of the channel, using positions for transmitting a portion of video control signals in the video output stream to transmit the data stream, and compressing the video output stream. The communication interface circuit may have another mode provided for mixing the video output stream and the data stream to transmit a mixed video output stream through the channel.

Abstract: A video processing circuit includes a video generating unit for generating a video output stream, a data generating unit (e.g. graphic generating unit) for providing a data stream (e.g. graphical stream), and a communication interface circuit. The communication interface circuit has a mode provided for merging the video output stream and the graphical stream to transmit a first merged signal through a channel. In the mode, the communication interface circuit merges the video output stream and the data stream by increasing a working frequency of the communication interface circuit to increase bandwidths of the channel, using positions for transmitting a portion of video control signals in the video output stream to transmit the data stream, and compressing the video output stream. The communication interface circuit may have another mode provided for mixing the video output stream and the data stream to transmit a mixed video output stream through the channel.

Abstract: A video processing circuit includes a video generating unit for generating a video output stream, a graphic generating unit for providing a graphical stream, and a communication interface circuit. The communication interface circuit has a first mode provided for mixing the video output stream and the graphical stream to transmit a mixed video output stream through a channel and a second mode provided for merging the video output stream and the graphical stream to transmit a first merged signal through the channel. In the second mode, the communication interface circuit merges the video output stream and the graphical stream by increasing a working frequency of the communication interface circuit to increase bandwidths of the channel, using positions for transmitting a portion of video control signals in the video output stream to transmit the graphical stream, and compressing the video output stream.

Abstract: A display apparatus has a housing, a base, a system board and a display panel. The base is connected to the housing such that the display apparatus is disposed on a flat surface. The system board is disposed in the housing and has a control system for performing an up-down inversing process for an image transmitted from a signal source. The display panel has a timing controller and a pixel array. Specifically, the display panel is put upside down in the housing such that the pixel array is also upside down, and the timing controller is adjacent to the location connecting the base with the housing. The timing controller is coupled to the system board, to perform a left-right mirroring process for the up-down inversed image.

Abstract: A video processing circuit includes a video generating unit for generating a video output stream, a graphic generating unit for providing a graphical stream, and a communication interface circuit. The communication interface circuit has a first mode provided for mixing the video output stream and the graphical stream to transmit a mixed video output stream through a channel and a second mode provided for merging the video output stream and the graphical stream to transmit a first merged signal through the channel. In the second mode, the communication interface circuit merges the video output stream and the graphical stream by increasing a working frequency of the communication interface circuit to increase bandwidths of the channel, using positions for transmitting a portion of video control signals in the video output stream to transmit the graphical stream, and compressing the video output stream.

Abstract: A display apparatus has a housing, a base, a system board and a display panel. The base is connected to the housing such that the display apparatus is disposed on a flat surface. The system board is disposed in the housing and has a control system for performing an up-down inversing process for an image transmitted from a signal source. The display panel has a timing controller and a pixel array. Specifically, the display panel is put upside down in the housing such that the pixel array is also upside down, and the timing controller is adjacent to the location connecting the base with the housing. The timing controller is coupled to the system board, to perform a left-right mirroring process for the up-down inversed image.

Abstract: A video processing circuit includes a video generating unit for generating a video output stream, a graphic generating unit for providing a graphical stream, and a communication interface circuit coupled to the video generating unit and the graphic generating unit. The communication interface circuit has a first mode provided for mixing the video output stream and the graphical stream to transmit a mixed video output stream through a channel and a second mode provided for merging the video output stream and the graphical stream to transmit a first merged signal through the channel. In the second mode, the communication interface circuit merges the video output stream and the graphical stream by increasing a working frequency of the communication interface circuit to increase bandwidths of the channel, using positions for transmitting a portion of video control signals in the video output stream to transmit the graphical stream, and compressing the video output stream.

Abstract: A signal processing apparatus for generating an output analog signal according to a raw digital signal is disclosed. The signal processing apparatus includes a DAC, a storage device, and an adjusting device. The storage device is utilized for storing a target mapping table equivalent to a combination of a predetermined correction mapping table and a DAC calibration mapping table corresponding to the DAC. The adjusting device is coupled to the DAC and the storage device, and is utilized for adjusting the raw digital signal to generate a calibrated digital signal according to the target mapping table stored in the storage device. The DAC converts the calibrated digital signal to generate the output analog signal.

Abstract: A parameter adjusting method of an image resizing module. The method includes receiving an image signal; and referencing a signal characteristic of the image signal to adjust a parameter with which the image resizing module resizes the image signal.

Abstract: Methods for obtaining a sampling phase to generate image information according to an analog image signal and timing information are performed. In an exemplary method, sampling clocks having a predetermined phase difference therebetween is sequentially generated according to timing information. The analog image signal is sampled using the sampling clocks, and sequential sampled values corresponding to each sampling clock are generated. The sampled values are detected to obtain edges formed by the sampled values. Magnitudes of the edges are accumulated to generate accumulation values. An optimum sampling clock is obtained according to the accumulation values. The optimum sampling clock corresponding to the accumulation value is the largest one among the accumulation values corresponding to the adjacent sampling clocks, and the difference among the accumulation values corresponding to the adjacent sampling clocks is within a predetermined range.

Abstract: Methods for obtaining a sampling phase to generate image information according to an analog image signal and timing information are performed. In an exemplary method, sampling clocks having a predetermined phase difference therebetween is sequentially generated according to timing information. The analog image signal is sampled using the sampling clocks, and sequential sampled values corresponding to each sampling clock are generated. The sampled values are detected to obtain edges formed by the sampled values. Magnitudes of the edges are accumulated to generate accumulation values. An optimum sampling clock is obtained according to the accumulation values. The optimum sampling clock corresponding to the accumulation value is the largest one among the accumulation values corresponding to the adjacent sampling clocks, and the difference among the accumulation values corresponding to the adjacent sampling clocks is within a predetermined range.