Abstract: A system for integrating triangle setup and attribute setup operations into a programmable execution unit of a graphics processing unit is disclosed. A method for integrating triangle setup and attribute setup operations into a programmable execution unit graphics processing unit is also disclosed. In one embodiment, at least one execution unit is configured for multi-threaded operation. The at least one execution unit is configured to execute at least one thread for triangle setup operations and attribute setup operations as well as threads for pixel shader, geometry shader and vertex shader operations.

Abstract: Various embodiments of shader processing systems and methods are disclosed. One method embodiment, among others, comprises a dependent texture read method executed using a multi-threaded, parallel computational core of a graphics processing unit (GPU). Such a method includes generating a dependent texture read request at logic configured to perform shader computations corresponding to a first thread, and sending shader-calculated, texture-sampling related parameters corresponding to the first thread to a texture pipeline while retaining at the logic all other shader processing related information corresponding to the first thread.

Abstract: The present disclosure provides for processing units, which are capable of concurrently executing instructions, and a source arbitrator. The source arbitrator determines whether instructions for the processing units are read from different sources. If the source arbitrator determines that each processing unit reads its respective instruction from a different source, then the instructions from the various sources are provided to their corresponding processing units for substantially concurrent processing.

Abstract: A method and a computing system are provided. The computing system may include a system memory configured to store data in a first data format. The computing system may also include a computational core comprising a plurality of execution units (EU). The computational core may be configured to request data from the system memory and to process data in a second data format. Each of the plurality of EU may include an execution control and datapath and a specialized L1 cache pool. The computing system may include a multipurpose L2 cache in communication with the each of the plurality of EU and the system memory. The multipurpose L2 cache may be configured to store data in the first data format and the second data format. The computing system may also include an orthogonal data converter in communication with at least one of the plurality of EU and the system memory.

Abstract: Provided is a system for managing multiple contexts in a decentralized graphics processing unit. The system includes multiple control units that can include a context buffer, a context processor, and a context scheduler. Also included is logic to receive multiple contexts, logic to identify at least one of the contexts, and logic to facilitate communication among the control units.

Abstract: A method for rendering a visible portion of an image that includes a plurality of graphics primitives. The size of the graphics primitives may be large and require the use of floating point numbers to represent the vertices. When the graphics primitives have a common vertex that is visible, the edge functions for the primitive are computed so as to avoid the common vertex becoming different for the different primitives. If the other vertices of the graphics primitives lie outside a bounding rectangle, then a vertex is formed at the intersection of the bounding rectangle and the graphics primitive. Fixed point numbers for the common vertex and other vertices including intersection vertices are then used to compute edge functions of the primitive and the primitive is rendered using the edge functions. If the common vertex is not visible, then floating point numbers are used to compute the edge functions.

Abstract: The present disclosure describes implementations for processing instructions and data across multiple Arithmetic Logic Units (ALUs). In one implementation, a graphics processing apparatus comprises a plurality of ALUs configured to process independent instructions in parallel. Pre-processing logic is configured to receive instructions and associated data to be directed to one of the plurality of ALUs for processing from a register file, the pre-processing logic being configured to selectively format received instructions for delivery to a plurality of the ALUs. In addition, post-processing logic is configured to receive data output from the plurality of the ALUs and deliver the received data to the register file for write-back, the post-processing logic being configured to selectively format data output from a plurality of the ALUs for delivery to the register file as though the data had been output by a single ALU.

Abstract: The present disclosure is directed to novel methods and apparatus for managing or performing the dynamic allocation or reallocation of processing resources among a vertex shader, a geometry shader, and pixel shader of a graphics processing unit. Specifically, embodiments of the invention embody or comprise plurality of execution units, wherein each execution unit is configured for multi-threaded operation. Logic is provided for receiving requests from each of a plurality of shader stages to perform shader-related computations, and scheduling threads within the plurality of execution units to perform the requested shader-related computations. The threads within the execution units of the pool are individually scheduled to perform shader-related computations, such that a given thread can be scheduled over time to perform shader operations for different shader stages.

Abstract: The present disclosure provides for processing units, which are capable of concurrently executing instructions, and a source arbitrator. The source arbitrator determines whether instructions for the processing units are read from different sources. If the source arbitrator determines that each processing unit reads its respective instruction from a different source, then the instructions from the various sources are provided to their corresponding processing units for substantially concurrent processing.

Abstract: A system and method for rendering a non-zero thickness line on a pixel-limited output device such that aliasing of the line is reduced. The edges defining a line segment are expanded to insure that any pixel touched by the line segment has its center included in the bounds of the line segment. The area of any pixel partially or fully covered by the expanded line is determined. If one edge of the line traverses the pixel, the area is determined according to whether a triangular or triangular plus parallelogram area is covered. If more than one edge of the line segment traverses a pixel, the area covered is computed based on the single edge case. With the area covered by the line segment known, the color or shading of the pixel is determined by linear interpolation between the line and the background.