Abstract: Units of shader work, such as warps or wavefronts, are grouped into clusters. An individual vector register file of a processor is operated as segments, where a segment may be independently operated in an active mode or a reduced power data retention mode. The scheduling of the clusters is selected so that a cluster is allocated a segment of the vector register file. Additional sequencing may be performed for a cluster to reach a synchronization point. Individual segments are placed into the reduced power data retention mode during a latency period when the cluster is waiting for execution of a request, such as a sample request.

Abstract: A method for computing in a thread-based environment provides manipulating an execution mask to enable and disable threads when executing multiple conditional function clauses for process instructions. Execution lanes are controlled based on execution participation for the process instructions for reducing resource consumption. Execution of particular one or more schedulable structures that include multiple process instructions are skipped based on the execution mask and activating instructions.

Abstract: Provided are patterned nanoporous gold (“P-NPG”) films that may act as at least one of an effective and stable surface-enhanced Raman scattering (“SERS”) substrate. Methods of fabricating the P-NPG films using a low-cost stamping technique are also provided. The P-NPG films may provide uniform SERS signal intensity and SERS signal intensity enhancement by a factor of at least about 1×107 relative to the SERS signal intensity from a non-enhancing surface.

Abstract: Units of shader work, such as warps or wavefronts, are grouped into clusters. An individual vector register file of a processor is operated as segments, where a segment may be independently operated in an active mode or a reduced power data retention mode. The scheduling of the clusters is selected so that a cluster is allocated a segment of the vector register file. Additional sequencing may be performed for a cluster to reach a synchronization point. Individual segments are placed into the reduced power data retention mode during a latency period when the cluster is waiting for execution of a request, such as a sample request.

Abstract: Output current ripple is reduced in a three-level DC-DC power converter by connecting a plurality of phase legs in parallel between a source of input power and an output of the power converter and conducting power from the source of input power to the power converter output in an interleaved manner. The large current that results from such interleaved operation is reduced to acceptable levels, potentially less than the output current ripple of the power converter by providing inversely coupled inductors having a mutual inductance preferably greater than the inductor of the power converter in respective phase legs and in series in the circulating current path to avoid any need to increase the power converter inductance due to the circulating current. The inductor and inversely coupled inductors are preferably integrated into a single magnetic element of compact design.

Abstract: An H-bridge micro inverter grid-connected device is invented to solve the problem that failure of any photovoltaic panel on the existing solar photovoltaic system cascade can cause efficiency reduction of the whole photovoltaic panel module. The H-bridge micro inverter grid-connected device comprises a single-chip microcomputer controller, a CPLD controller, a MOSFET full-bridge circuit, a high-frequency transformer, a half-bridge rectifying circuit, an SCR full-bridge circuit and a filter circuit, wherein the MOSFET full-bridge circuit is in the full-bridge type, the high-frequency transformer is a single-phase transformer with a central tap, and the SCR full-bridge circuit is applied. The integral structure above is characterized by the decreasing number of components, the reduction of power switches, and the simplification of the control circuits and driving circuits, so as to decrease the number of full-control switch components, improve the system reliability and reduce the system costs.

Abstract: A method for processing pixel information includes pushing pixel varying attributes to a register file of a shader processing element. At least a portion of the pixel varying attributes are pulled based on a control flow in the shader processing element. At least a portion of the pixel varying attributes are interpolated.

Abstract: A method for computing in a thread-based environment provides manipulating an execution mask to enable and disable threads when executing multiple conditional function clauses for process instructions. Execution lanes are controlled based on execution participation for the process instructions for reducing resource consumption. Execution of particular one or more schedulable structures that include multiple process instructions are skipped based on the execution mask and activating instructions.

Abstract: Provided are methods for imprinting a porous material, the methods including applying a first stamp to a porous material having an average pore size of less than about 100 ?m, the first stamp having at least a first portion having a first height, a second portion having a second height and a third portion having a third height, wherein the first height, second height and third height are different.

Abstract: An H-bridge micro inverter grid-connected device is invented to solve the problem that failure of any photovoltaic panel on the existing solar photovoltaic system cascade can cause efficiency reduction of the whole photovoltaic panel module. The H-bridge micro inverter grid-connected device comprises a single-chip microcomputer controller, a CPLD controller, a MOSFET full-bridge circuit, a high-frequency transformer, a half-bridge rectifying circuit, an SCR full-bridge circuit and a filter circuit, wherein the MOSFET full-bridge circuit is in the full-bridge type, the high-frequency transformer is a single-phase transformer with a central tap, and the SCR full-bridge circuit is applied. The integral structure above is characterized by the decreasing number of components, the reduction of power switches, and the simplification of the control circuits and driving circuits, so as to decrease the number of full-control switch components, improve the system reliability and reduce the system costs.

Abstract: Provided are patterned nanoporous gold (“P-NPG”) films that may act as at least one of an effective and stable surface-enhanced Raman scattering (“SERS”) substrate. Methods of fabricating the P-NPG films using a low-cost stamping technique are also provided. The P-NPG films may provide uniform SERS signal intensity and SERS signal intensity enhancement by a factor of at least about 1×107 relative to the SERS signal intensity from a non-enhancing surface.

Abstract: A seek-and-scan probe memory device comprising a patterned capping layer over a phase-change media, where the patterned capping layer defines the bit locations on the phase-change media. The patterned capping layer may be formed from self-assembled structures. In other embodiments, nanostructures are formed on the bottom electrode below the phase-change media to focus an applied electric field from the probe, so as to increase bit density and contrast. The nanostructures may be a regular or random array of nanostructures, formed by using a self-assembling material. The nanostructures may be conductive or non-conductive. Other embodiments are described and claimed.

Abstract: Provided is an instruction set for a dual-mode computer processing environment that includes instructions divided into multiple instruction groups. The instructions include mode-specific fields, common fields, and group-specific fields. Also a method for encoding an instruction set in a dual-mode computer processing environment is provided. The method includes dividing the instruction set into a instruction groups and defining common fields, group-specific fields, mode-specific fields, and mode-configurable fields.

Abstract: The present disclosure is directed to novel methods and apparatus for managing or performing the dynamic allocation or reallocation of processing resources among a vertex shader, a geometry shader, and pixel shader of a graphics processing unit. In one embodiment a method for graphics processing comprises assigning at least one execution unit to each of a plurality of shader units, the plurality of shader units comprising a vertex shader, a geometry shader, and a pixel shader, wherein an execution unit assigned to a given shader unit performs processing tasks for only that shader unit, determining that one of the plurality of shader units is bottlenecked, and reassigning at least one execution unit from a non-bottlenecked shader unit to the shader unit determined to be bottlenecked.

Abstract: The present disclosure relates to caches that are capable of improving processor performance. In some embodiments, among others, incoming requests are compared to determine whether or not those requests match. In the event that the incoming requests match, the matching requests are merged. For other embodiments, an incoming request is compared to a previous entry to determine whether the request matches the entry. In the event that the request matches the entry, the request and the entry are merged. These entries may originate from the same cache line, or, alternatively, may originate from different cache lines.

Abstract: The present disclosure relates to caches that are capable of improving processor performance. In some embodiments, among others, a cache request is received, and logic within the cache determines whether the received cache request results in a hit on the cache. If the cache request results in a hit on the cache, then that cache request is serviced. Conversely, if the cache request does not result in a hit (e.g., miss, miss-on-miss, hit-on-miss, etc.), then information related to the received cache request is stored in a missed request table. For some embodiments, missed read requests are stored in a missed read request table, while missed write requests are stored in a missed write request table.

Abstract: A method for rendering a visible portion of an image that includes a plurality of graphics primitives. The size of the graphics primitives may be large and require the use of floating point numbers to represent the vertices. When the graphics primitives have a common vertex that is visible, the edge functions for the primitive are computed so as to avoid the common vertex becoming different for the different primitives. If the other vertices of the graphics primitives lie outside a bounding rectangle, then a vertex is formed at the intersection of the bounding rectangle and the graphics primitive. Fixed point numbers for the common vertex and other vertices including intersection vertices are then used to compute edge functions of the primitive and the primitive is rendered using the edge functions. If the common vertex is not visible, then floating point numbers are used to compute the edge functions.

Abstract: A system and method for rendering a non-zero thickness line on a pixel-limited output device such that aliasing of the line is reduced. The edges defining a line segment are expanded to insure that any pixel touched by the line segment has its center included in the bounds of the line segment. The area of any pixel partially or fully covered by the expanded line is determined. If one edge of the line traverses the pixel, the area is determined according to whether a triangular or triangular plus parallelogram area is covered. If more than one edge of the line segment traverses a pixel, the area covered is computed based on the single edge case. With the area covered by the line segment known, the color or shading of the pixel is determined by linear interpolation between the line and the background.