Patents by Inventor Yang-Ju Lu
Yang-Ju Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220084878Abstract: A fabricating method of transistors includes providing a substrate with numerous transistors thereon. Each of the transistors includes a gate structure. A gap is disposed between gate structures adjacent to each other. Later, a protective layer and a first dielectric layer are formed in sequence to cover the substrate and the transistors and to fill in the gap. Next, numerous buffering particles are formed to contact the first dielectric layer. The buffering particles do not contact each other. Subsequently, a second dielectric layer is formed to cover the buffering particles. After that, a first planarization process is performed to remove part of the first dielectric layer, part of the second dielectric layer and buffering particles by taking the protective layer as a stop layer, wherein a removing rate of the second dielectric layer is greater than a removing rate of the buffering particles during the first planarization process.Type: ApplicationFiled: September 17, 2020Publication date: March 17, 2022Inventors: Fu-Shou Tsai, Yang-Ju Lu, Yong-Yi Lin, Yu-Lung Shih, Ching-Yang Chuang, Ji-Min Lin, Kun-Ju Li
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Patent number: 11257711Abstract: A fabricating method of transistors includes providing a substrate with numerous transistors thereon. Each of the transistors includes a gate structure. A gap is disposed between gate structures adjacent to each other. Later, a protective layer and a first dielectric layer are formed in sequence to cover the substrate and the transistors and to fill in the gap. Next, numerous buffering particles are formed to contact the first dielectric layer. The buffering particles do not contact each other. Subsequently, a second dielectric layer is formed to cover the buffering particles. After that, a first planarization process is performed to remove part of the first dielectric layer, part of the second dielectric layer and buffering particles by taking the protective layer as a stop layer, wherein a removing rate of the second dielectric layer is greater than a removing rate of the buffering particles during the first planarization process.Type: GrantFiled: September 17, 2020Date of Patent: February 22, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Fu-Shou Tsai, Yang-Ju Lu, Yong-Yi Lin, Yu-Lung Shih, Ching-Yang Chuang, Ji-Min Lin, Kun-Ju Li
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Patent number: 11211471Abstract: The present invention discloses a metal gate process. A sacrificial nitride layer is introduced during the fabrication of metal gates. The gate height can be well controlled by introducing the sacrificial nitride layer. Further, the particle fall-on problem can be effectively solved.Type: GrantFiled: September 10, 2020Date of Patent: December 28, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Fu-Shou Tsai, Yong-Yi Lin, Yang-Ju Lu, Yu-Lung Shih, Ji-Min Lin, Ching-Yang Chuang, Kun-Ju Li
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Patent number: 11139384Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region, a second region, a third region, and a fourth region; forming a tuning layer on the second region; forming a first work function metal layer on the first region and the tuning layer of the second region; forming a second work function metal layer on the first region, the second region, and the fourth region; and forming a top barrier metal (TBM) layer on the first region, the second region, the third region, and the fourth region.Type: GrantFiled: September 4, 2019Date of Patent: October 5, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Chih Lai, Yun-Tzu Chang, Wei-Ming Hsiao, Nien-Ting Ho, Shih-Min Chou, Yang-Ju Lu, Ching-Yun Chang, Yen-Chen Chen, Kuan-Chun Lin, Chi-Mao Hsu
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Publication number: 20210273076Abstract: A method of forming a gate includes the following steps. A gate structure is formed on a substrate. An etch stop layer is formed on the gate structure and the substrate. A dielectric layer is formed to cover the etch stop layer. The dielectric layer is planarized to form a planarized top surface of the dielectric layer and expose a portion of the etch stop layer on the gate structure. An oxygen containing treatment is performed to form an oxygen containing layer on the exposed etch stop layer. A deposition process is performed to form an oxide layer covering the planarized top surface of the dielectric layer and the oxygen containing layer.Type: ApplicationFiled: February 27, 2020Publication date: September 2, 2021Inventors: Yang-Ju Lu, Chun-Yi Wang, Fu-Shou Tsai, Yong-Yi Lin, Ching-Yang Chuang, Wen-Chin Lin, Hsin-Kuo Hsu
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Publication number: 20200006514Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region, a second region, a third region, and a fourth region; forming a tuning layer on the second region; forming a first work function metal layer on the first region and the tuning layer of the second region; forming a second work function metal layer on the first region, the second region, and the fourth region; and forming a top barrier metal (TBM) layer on the first region, the second region, the third region, and the fourth region.Type: ApplicationFiled: September 4, 2019Publication date: January 2, 2020Inventors: Kuo-Chih Lai, Yun-Tzu Chang, Wei-Ming Hsiao, Nien-Ting Ho, Shih-Min Chou, Yang-Ju Lu, Ching-Yun Chang, Yen-Chen Chen, Kuan-Chun Lin, Chi-Mao Hsu
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Patent number: 10490643Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region, a second region, a third region, and a fourth region; forming a tuning layer on the second region; forming a first work function metal layer on the first region and the tuning layer of the second region; forming a second work function metal layer on the first region, the second region, and the fourth region; and forming a top barrier metal (TBM) layer on the first region, the second region, the third region, and the fourth region.Type: GrantFiled: November 24, 2015Date of Patent: November 26, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Chih Lai, Yun-Tzu Chang, Wei-Ming Hsiao, Nien-Ting Ho, Shih-Min Chou, Yang-Ju Lu, Ching-Yun Chang, Yen-Chen Chen, Kuan-Chun Lin, Chi-Mao Hsu
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Patent number: 10340350Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes an isolation layer, a gate dielectric layer, a tantalum nitride layer, a tantalum oxynitride layer, an n type work function metal layer and a filling metal. The isolation layer is formed on a substrate, and the isolation layer has a first gate trench. The gate dielectric layer is formed in the first gate trench, the tantalum nitride layer is formed on the gate dielectric layer, and the tantalum oxynitride layer is formed on the tantalum nitride layer. The n type work function metal layer is formed on the tantalum oxynitride layer in the first gate trench, and the filling metal is formed on the n type work function metal layer in the first gate trench.Type: GrantFiled: July 25, 2018Date of Patent: July 2, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shih-Min Chou, Yun-Tzu Chang, Wei-Ning Chen, Wei-Ming Hsiao, Chia-Chang Hsu, Kuo-Chih Lai, Yang-Ju Lu, Yen-Chen Chen, Chun-Yao Yang
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Publication number: 20180331193Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes an isolation layer, a gate dielectric layer, a tantalum nitride layer, a tantalum oxynitride layer, an n type work function metal layer and a filling metal. The isolation layer is formed on a substrate, and the isolation layer has a first gate trench. The gate dielectric layer is formed in the first gate trench, the tantalum nitride layer is formed on the gate dielectric layer, and the tantalum oxynitride layer is formed on the tantalum nitride layer. The n type work function metal layer is formed on the tantalum oxynitride layer in the first gate trench, and the filling metal is formed on the n type work function metal layer in the first gate trench.Type: ApplicationFiled: July 25, 2018Publication date: November 15, 2018Inventors: Shih-Min Chou, Yun-Tzu Chang, Wei-Ning Chen, Wei-Ming Hsiao, Chia-Chang Hsu, Kuo-Chih Lai, Yang-Ju Lu, Yen-Chen Chen, Chun-Yao Yang
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Publication number: 20180261675Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes an isolation layer, a gate dielectric layer, a tantalum nitride layer, a tantalum oxynitride layer, an n type work function metal layer and a filling metal. The isolation layer is formed on a substrate, and the isolation layer has a first gate trench. The gate dielectric layer is formed in the first gate trench, the tantalum nitride layer is formed on the gate dielectric layer, and the tantalum oxynitride layer is formed on the tantalum nitride layer. The n type work function metal layer is formed on the tantalum oxynitride layer in the first gate trench, and the filling metal is formed on the n type work function metal layer in the first gate trench.Type: ApplicationFiled: March 8, 2017Publication date: September 13, 2018Inventors: Shih-Min Chou, Yun-Tzu Chang, Wei-Ning Chen, Wei-Ming Hsiao, Chia-Chang Hsu, Kuo-Chih Lai, Yang-Ju Lu, Yen-Chen Chen, Chun-Yao Yang
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Patent number: 10074725Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes an isolation layer, a gate dielectric layer, a tantalum nitride layer, a tantalum oxynitride layer, an n type work function metal layer and a filling metal. The isolation layer is formed on a substrate, and the isolation layer has a first gate trench. The gate dielectric layer is formed in the first gate trench, the tantalum nitride layer is formed on the gate dielectric layer, and the tantalum oxynitride layer is formed on the tantalum nitride layer. The n type work function metal layer is formed on the tantalum oxynitride layer in the first gate trench, and the filling metal is formed on the n type work function metal layer in the first gate trench.Type: GrantFiled: March 8, 2017Date of Patent: September 11, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shih-Min Chou, Yun-Tzu Chang, Wei-Ning Chen, Wei-Ming Hsiao, Chia-Chang Hsu, Kuo-Chih Lai, Yang-Ju Lu, Yen-Chen Chen, Chun-Yao Yang
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Patent number: 9966425Abstract: A method for fabricating a metal-insulator-metal (MIM) capacitor includes the steps of: forming a capacitor bottom metal (CBM) layer on a material layer; forming a silicon layer on the CBM layer; forming a capacitor dielectric layer on the silicon layer; and forming a capacitor top metal (CTM) layer on the capacitor dielectric layer.Type: GrantFiled: February 28, 2017Date of Patent: May 8, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Jen-Po Huang, Chin-Fu Lin, Bin-Siang Tsai, Xu Yang Shen, Seng Wah Liau, Yen-Chen Chen, Ko-Wei Lin, Chun-Ling Lin, Kuo-Chih Lai, Ai-Sen Liu, Chun-Yuan Wu, Yang-Ju Lu
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Patent number: 9728467Abstract: A method for modulating a work function of a semiconductor device having a metal gate structure including the following steps is provided. A first stacked gate structure and a second stacked gate structure having an identical structure are provided on a substrate. The first stacked gate structure and the second stacked gate structure respectively include a first work function metal layer of a first type. A patterned hard mask layer is formed. The patterned hard mask layer exposes the first work function metal layer of the first stacked gate structure and covers the first work function metal layer of the second stacked gate structure. A first gas treatment is performed to the first work function metal layer of the first stacked gate structure exposed by the patterned hard mask layer. A gas used in the first gas treatment includes nitrogen-containing gas or oxygen-containing gas.Type: GrantFiled: October 12, 2015Date of Patent: August 8, 2017Assignee: United Microelectronics Corp.Inventors: Yun-Tzu Chang, Shih-Min Chou, Kuo-Chih Lai, Ching-Yun Chang, Hsiang-Chieh Yen, Yen-Chen Chen, Yang-Ju Lu, Nien-Ting Ho, Chi-Mao Hsu
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Patent number: 9691704Abstract: A semiconductor structure comprises a first wire level, a second wire level and a via level. The first wire level comprises a first conductive feature. The second wire level is disposed on the first wire level. The second wire level comprises a second conductive feature and a third conductive feature. The via level is disposed between the first wire level and the second wire level. The via level comprises a via connecting the first conductive feature and the second conductive feature. There is a first air gap between the first conductive feature and the second conductive feature. There is a second air gap between the second conductive feature and the third conductive feature. The first air gap and the second air gap are linked.Type: GrantFiled: June 7, 2016Date of Patent: June 27, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Chih Lai, Chia-Chang Hsu, Nien-Ting Ho, Ching-Yun Chang, Yen-Chen Chen, Shih-Min Chou, Yun-Tzu Chang, Yang-Ju Lu, Wei-Ming Hsiao, Wei-Ning Chen
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Publication number: 20170148891Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region, a second region, a third region, and a fourth region; forming a tuning layer on the second region; forming a first work function metal layer on the first region and the tuning layer of the second region; forming a second work function metal layer on the first region, the second region, and the fourth region; and forming a top barrier metal (TBM) layer on the first region, the second region, the third region, and the fourth region.Type: ApplicationFiled: November 24, 2015Publication date: May 25, 2017Inventors: Kuo-Chih Lai, Yun-Tzu Chang, Wei-Ming Hsiao, Nien-Ting Ho, Shih-Min Chou, Yang-Ju Lu, Ching-Yun Chang, Yen-Chen Chen, Kuan-Chun Lin, Chi-Mao Hsu
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Publication number: 20170076995Abstract: A method for modulating a work function of a semiconductor device having a metal gate structure including the following steps is provided. A first stacked gate structure and a second stacked gate structure having an identical structure are provided on a substrate. The first stacked gate structure and the second stacked gate structure respectively include a first work function metal layer of a first type. A patterned hard mask layer is formed. The patterned hard mask layer exposes the first work function metal layer of the first stacked gate structure and covers the first work function metal layer of the second stacked gate structure. A first gas treatment is performed to the first work function metal layer of the first stacked gate structure exposed by the patterned hard mask layer. A gas used in the first gas treatment includes nitrogen-containing gas or oxygen-containing gas.Type: ApplicationFiled: October 12, 2015Publication date: March 16, 2017Inventors: Yun-Tzu Chang, Shih-Min Chou, Kuo-Chih Lai, Ching-Yun Chang, Hsiang-Chieh Yen, Yen-Chen Chen, Yang-Ju Lu, Nien-Ting Ho, Chi-Mao Hsu
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Patent number: 9576803Abstract: The present invention provides a method for metal gate work function tuning before contact formation in a fin-shaped field effect transistor (FinFET), where in the method comprises the following steps. (S1) providing a substrate having a metal gate structure on a side of the substrate, (S2) forming a titanium nitride (TiN) layer on the side of the substrate, and (S3) performing a gate annealing to tune work function of the metal gate structure.Type: GrantFiled: May 13, 2015Date of Patent: February 21, 2017Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Kuo-Chih Lai, Yang-Ju Lu, Ching-Yun Chang, Yen-Chen Chen, Shih-Min Chou, Yun Tzu Chang, Fang-Yi Liu, Hsiang-Chieh Yen, Nien-Ting Ho
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Publication number: 20160336181Abstract: The present invention provides a method for metal gate work function tuning before contact formation in a fin-shaped field effect transistor (FinFET), where in the method comprises the following steps. (S1) providing a substrate having a metal gate structure on a side of the substrate, (S2) forming a titanium nitride (TiN) layer on the side of the substrate, and (S3) performing a gate annealing to tune work function of the metal gate structure.Type: ApplicationFiled: May 13, 2015Publication date: November 17, 2016Inventors: KUO-CHIH LAI, YANG-JU LU, CHING-YUN CHANG, YEN-CHEN CHEN, SHIH-MIN CHOU, YUN TZU CHANG, FANG-YI LIU, HSIANG-CHIEH YEN, NIEN-TING HO
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Patent number: 9478628Abstract: A metal gate forming process includes the following steps. A first metal layer is formed on a substrate by at least a first step followed by a second step, wherein the processing power of the second step is higher than the processing power of the first step.Type: GrantFiled: September 14, 2015Date of Patent: October 25, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Chih Lai, Nien-Ting HO, Chi-Mao Hsu, Ching-Yun Chang, Yen-Chen Chen, Yang-Ju Lu, Shih-Min Chou, Yun-Tzu Chang, Hsiang-Chieh Yen, Min-Chuan Tsai